Multi-channel analog to digital converter

Patent metadata

Field	Value
Publication number	US-9748964-B1
Application number	US-201615362869-A
Country	US
Kind code	B1
Filing date	Nov 29, 2016
Priority date	Nov 29, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Embodiments of a multi-channel analog to digital converter (ADC) include: a first multiplying digital to analog converter (MDAC) having: first and second switched capacitor circuit paths respectively coupled between first and second input nodes and an input node of a first gain element, a second MDAC having: third and fourth switched capacitor circuit paths respectively coupled between third and fourth input nodes and an input node of a second gain element, a third MDAC having: fifth and sixth switched capacitor circuit paths respectively coupled between a fifth input node and an input node of a third gain element, seventh and eighth switched capacitor circuit paths respectively coupled between a sixth input node and the input node of the third gain element, the fifth input node coupled to an output node of the first gain element, the sixth input node coupled to an output node of the second gain element.

First claim

What is claimed is:

1. A multi-channel analog to digital converter (ADC) comprising:
a first multiplying digital to analog converter (MDAC) comprising:
a first switched capacitor circuit path coupled between a first input node and an input node of a first gain element,
a second switched capacitor circuit path coupled between a second input node and the input node of the first gain element;

a second MDAC comprising:
a third switched capacitor circuit path coupled between a third input node and an input node of a second gain element,
a fourth switched capacitor circuit path coupled between a fourth input node and the input node of the second gain element;

a third MDAC comprising:
a fifth switched capacitor circuit path coupled between a fifth input node and an input node of a third gain element,
a sixth switched capacitor circuit path coupled between the fifth input node and the input node of the third gain element,
a seventh switched capacitor circuit path coupled between a sixth input node and the input node of the third gain element,
a eighth switched capacitor circuit path coupled between the sixth input node and the input node of the third gain element;

wherein the fifth input node is coupled to an output node of the first gain element, and the sixth input node is coupled to an output node of the second gain element.

2. The multi-channel ADC of claim 1 , wherein
the first, second, third, and fourth input nodes are respectively coupled to first, second, third, and fourth input channels,
the first MDAC is configured to sample the first and second input channels at a system clock rate,
the second MDAC is configured to sample the third and fourth input channels at the system clock rate, and
the first and second MDACs are each configured to operate at one half the system clock rate.

3. The multi-channel ADC of claim 1 , wherein
the first, second, third, and fourth input nodes are each tied to a single input channel,
the first and second MDACs are configured to sample the single input channel at twice a system clock rate, and
the first and second MDACs are each configured to operate at one half the system clock rate.

4. The multi-channel ADC of claim 1 , wherein
the first and second MDACs are configured to operate at a first frequency,
the third MDAC is configured to operate at a second frequency that is twice the first frequency.

5. The multi-channel ADC of claim 1 , further comprising:
a switching architecture configured to:
cause the first switched capacitor circuit path to sample a first voltage at the first input node and cause the second switched capacitor circuit path to provide a second voltage to the input node of the first gain element during a first time period,
cause the first switched capacitor circuit path to provide the first voltage to the input node of the first gain element and cause the second switched capacitor circuit path to sample another second voltage at the second input node during a second time period.

6. The multi-channel ADC of claim 5 , wherein
the switching architecture is further configured to:
cause the third switched capacitor circuit path to sample a third voltage at the third input node and cause the fourth switched capacitor circuit path to provide a fourth voltage to the input node of the second gain element during a third time period,
cause the third switched capacitor circuit path to provide the third voltage to the input node of the second gain element and cause the fourth switched capacitor circuit path to sample another fourth voltage at the fourth input node during a fourth time period.

7. The multi-channel ADC of claim 6 , wherein
the third time period begins after the first time period begins, and the fourth time period begins after the second time period begins.

8. The multi-channel ADC of claim 6 , wherein
the third time period begins after the first time period ends, and the fourth time period begins after the second time period ends.

9. The multi-channel ADC of claim 1 , wherein
the first, second, third, and fourth input nodes are respectively associated with first, second, third, and fourth sampling channels,
the first gain element outputs a sequence of time-interleaved first output voltages, each first output voltage alternately associated with the first and second sampling channels,
the second gain element outputs a sequence of time-interleaved second output voltages, each second output voltage alternately associated with the third and fourth sampling channels,
the first and second gain elements respectively output the first and second output voltages in an alternating manner.

10. The multi-channel ADC of claim 9 , wherein
the third gain element outputs a sequence of time-interleaved third output voltages, each output voltage sequentially associated with the first, second, third, and fourth sampling channels.

11. The multi-channel ADC of claim 1 , further comprising:
a fourth MDAC comprising:
a ninth switched capacitor circuit path coupled between a seventh input node and an input node of a fourth gain element,
a tenth switched capacitor circuit path coupled between the seventh input node and the input node of the fourth gain element,
a eleventh switched capacitor circuit path coupled between the seventh input node and the input node of the fourth gain element,
a twelfth switched capacitor circuit path coupled between the seventh input node and the input node of the fourth gain element;

wherein the seventh input node is coupled to an output node of the third gain element.

12. The multi-channel ADC of claim 1 , wherein
the first MDAC receives first and second clock phase signals and delayed first and second clock phase signals,
the first and second switched capacitor circuit paths are controlled to have alternating sample and gain phases by switches controlled by the delayed first and second clock phase signals,
the second MDAC receives third and fourth clock phase signals and delayed third and fourth clock phase signals, and
the third and fourth switched capacitor circuit paths are controlled to have alternating sample and gain phases by switches controlled by the delayed third and fourth clock phase signals.

13. The multi-channel ADC of claim 12 , wherein
the first and second clock phase signals are non-overlapping and the delayed first and second clock phase signals are non-overlapping with respect to one another,
the third and fourth clock phase signals are non-overlapping and the delayed first and second clock phase signals are non-overlapping with respect to one another.

14. The multi-channel ADC of claim 12 , wherein
the first, second, third, and fourth clock phase signals are non-overlapping and the delayed first, second, third, and fourth clock phase signals are non-overlapping with respect to one another.

15. The multi-channel ADC of claim 12 , wherein
the third MDAC receives the delayed first, second, third, and fourth clock phase signals, fifth, sixth, seventh, and eighth clock phase signals, and delayed fifth, sixth, seventh, and eighth clock phase signals,
the fifth, sixth, seventh, and eighth clock phase signals are non-overlapping with respect to one another and the delayed fifth, sixth, seventh, and eighth clock phase signals are non-overlapping with respect to one another.

16. An analog to digital conversion method comprising:
alternately sampling a first input node and a second input node as controlled by first and second clock phase signals that are non-overlapping with respect to one another, and
alternately generating a first output volt

Assignees

• Nxp Usa Inc

Inventors

• Kabir Mohammad Nizam
• Garrity Doug
• Hoseini Mariam
• Shiwale Rakesh

Classifications

• H03M1/001

  Analogue/digital/analogue conversion · CPC title

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/804

  with charge redistribution · CPC title