Switching circuit

Patent metadata

Field	Value
Publication number	US-9748951-B2
Application number	US-201615195707-A
Country	US
Kind code	B2
Filing date	Jun 28, 2016
Priority date	Jun 30, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A conversion circuit is disclosed. In one aspect, the conversion circuit includes a first input terminal for receiving a digital signal. The conversion circuit includes a second input terminal for receiving a bias voltage signal. The conversion circuit includes an output terminal for outputting a current. The conversion circuit includes a first and a second switch transistor connected to the first input terminal for receiving the digital signal. The conversion circuit includes a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal. The conversion circuit further includes a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor. The conversion circuit further includes a second branch, wherein the second current source transistor is connected to the output terminal via the second switch transistor.

First claim

What is claimed is:

1. A conversion circuit, comprising:
a first input terminal for receiving a digital signal;
a second input terminal for receiving a bias voltage signal;
an output terminal for outputting a current;
a first and a second switch transistor connected to the first input terminal for receiving said digital signal;
a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal;
a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor; and
a second branch wherein the second current source transistor is connected to the output terminal via the second switch transistor.

2. The conversion circuit of claim 1 , further comprising a transistor in cascade arranged for being fed with the current output via the output terminal.

3. The conversion circuit of claim 1 , wherein the output terminal comprises:
a first output terminal in the first branch; and
a second output terminal in the second branch.

4. The conversion circuit of claim 1 , wherein the digital signal is a modulated local oscillator signal.

5. The conversion circuit of claim 1 , further arranged for adding a bleeder current.

6. A device comprising a conversion circuit as in claim 1 .

7. A device comprising a plurality of conversion circuits as in claim 1 , the conversion circuits being arranged in parallel.

8. The device of claim 6 , further comprising a bias circuit arranged for generating the bias voltage signal, the bias circuit comprising a decoupling capacitance at its an output of the bias circuit.

9. The device of claim 7 , wherein the digital signal is a phase modulated RF signal so that the device can act as a polar digital transmitter.

10. A system comprising a first and a second device as in claim 7 , adapted for modulating an in-phase and a quadrature signal, respectively, so that the device can act as a Cartesian RF digital-to-analog converter.

11. A conversion circuit, comprising:
a first input terminal for receiving a digital signal;
a second input terminal for receiving a bias voltage signal;
an output terminal for outputting a current;
a first and a second switch transistor connected to the first input terminal for receiving said digital signal;
a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal, wherein the gate-source capacitance of the first current source transistor is substantially equal to the gate-drain capacitance of the second current source transistor;
a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor; and
a second branch wherein second current source transistor is connected to the output terminal via the second switch transistor.

12. The conversion circuit of claim 11 , wherein the ratio of the size of the first current source transistor to the size of the second current source transistor is about 1 to 3.

13. The conversion circuit of claim 11 , further comprising a transistor in cascode arranged for being fed with the current output via the output terminal.

14. The conversion circuit of claim 11 , wherein the output terminal comprises:
a first output terminal in the first branch; and
a second output terminal in the second branch.

15. The conversion circuit of claim 11 , wherein the digital signal is a modulated local oscillator signal.

16. The conversion circuit of claim 11 , further arranged for adding a bleeder current.

17. A device comprising a conversion circuit as in claim 11 .

18. A device comprising a plurality of conversion circuits as in claim 11 , the conversion circuits being arranged in parallel.

19. The device of claim 17 , further comprising a bias circuit arranged for generating the bias voltage signal, the bias circuit comprising a decoupling capacitance at an output of the bias circuit.

Assignees

• Imec Vzw

Inventors

• Zhang Xiaoqiang
• Ingels Mark

Classifications

• H03F2200/324

  An amplitude modulator or demodulator being used in the amplifier circuit · CPC title

• H03F1/14

  by use of neutralising means · CPC title

• H03M1/0863 Primary

  of switching transients, e.g. glitches · CPC title

• H03F2200/336

  A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit · CPC title

• H03F2200/525

  the bias or supply voltage or current of the source side of a FET amplifier being controlled to be on or off by a switch · CPC title