RF replicator for accurate modulated amplitude and phase measurement

Patent metadata

Field	Value
Publication number	US-9748905-B2
Application number	US-201414216560-A
Country	US
Kind code	B2
Filing date	Mar 17, 2014
Priority date	Mar 15, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

The disclosure provides a communication circuit including an amplification circuit, a replicator circuit, and a correction circuit. Specifically, the amplification circuit generates an amplified signal. The replicator circuit emulates the amplification circuit and generates a replicated signal that approximates the amplified signal. The replicated signal is used by the correction circuit to generate control signals for controlling the amplification circuit.

First claim

What is claimed is:

1. A communication circuit comprising:
an amplification circuit configured to receive an input signal, to generate a sensed signal, and to generate an amplified signal;
a replicator circuit configured to receive the sensed signal from the amplification circuit, and to generate a replicated signal approximately equal to the amplified signal; and
a correction circuit configured to receive the replicated signal, to generate a control signal, and to send the control signal to the amplification circuit such that the replicator circuit and the correction circuit form a control loop.

2. The communication circuit of claim 1 , wherein the replicator circuit includes a replicator transistor configured to emulate an amplification transistor in the amplification circuit, and wherein an active area of the replicator transistor is at least ten times smaller than an active area of the amplification transistor.

3. The communication circuit of claim 1 , further comprising:
a voltage matching circuit configured to provide a matched signal to the replicator circuit.

4. The communication circuit of claim 3 , wherein the voltage matching circuit includes a switching circuit configured to pass a first bias voltage from the amplification circuit to the replicator circuit when an input signal to the amplification circuit is high.

5. The communication circuit of claim 4 , further comprising:
a capacitance matching circuit, wherein the capacitance matching circuit includes:
a varactor bias; and
a varactor controlled by the varactor bias, and

wherein the varactor is coupled to a signal path at the replicator circuit.

6. The communication circuit of claim 3 , wherein the voltage matching circuit includes an offset circuit.

7. The communication circuit of claim 1 , further comprising:
a capacitor compensation circuit configured to replicate a nonlinear capacitance from the amplification circuit.

8. The communication circuit of claim 1 , wherein the replicator circuit is optimized to accurately replicate an amplitude of the amplification circuit.

9. The communication circuit of claim 1 , wherein the replicator circuit is optimized to accurately replicate a phase of the amplification circuit.

10. The communication circuit of claim 1 , further comprising:
a total radiated power circuit configured to send a total radiated power signal to the correction circuit.

11. The communication circuit of claim 1 , wherein the correction circuit includes a gain correction circuit and a phase correction circuit.

12. The communication circuit of claim 11 , wherein the gain correction circuit and the phase correction circuit share the replicated signal from the replicator circuit.

13. The communication circuit of claim 11 , further comprising:
an additional replicator circuit configured to generate an additional replicated signal, and
wherein the gain correction circuit receives the replicated signal, and
wherein the phase correction circuit receives the additional replicated signal.

14. The communication circuit of claim 1 , wherein the replicator circuit is configured for use in a circuit with intermittent operation.

15. A communication circuit comprising:
an amplification circuit; and
a replicator circuit associated with the amplification circuit, the replicator circuit including:
a first replicator transistor;
a second replicator transistor stacked above the first replicator transistor, and
a third replicator transistor stacked above the second replicator transistor, and

wherein the first replicator transistor has a smaller first active area than a first amplification transistor in the amplification circuit,
wherein the second replicator transistor has smaller second active area than a second amplification transistor in the amplification circuit, and
wherein the third replicator transistor has a smaller third active area than a third amplification transistor in the amplification circuit.

16. The communication circuit of claim 15 , further comprising:
a voltage matching circuit coupled to a gate of the first replicator transistor, wherein the voltage matching circuit includes a switching circuit.

17. The communication circuit of claim 16 , wherein the switching circuit is configured to pass a first bias voltage to a gate of the first replicator transistor whenever an input signal to the amplification circuit is high.

18. The communication circuit of claim 15 ,
wherein a gate of the first replicator transistor is coupled directly to a gate of the first amplification transistor,
wherein a gate of the second replicator transistor is coupled directly to a gate of the second amplification transistor; and
wherein a gate of the third replicator transistor is coupled to a gate of the third amplification transistor through a voltage matching circuit.

19. The communication circuit of claim 15 , further comprising:
a varactor bias circuit; and
a varactor controlled by the varactor bias circuit and coupled to a source of the first replicator transistor.

20. A communication circuit comprising:
an amplification circuit configured to receive an input signal, to generate a first intermediate signal, a second intermediate signal, and to generate an amplified signal, wherein the amplified signal includes a first fundamental component;
a replicator circuit configured to receive the input signal, to receive the second intermediate signal, and to generate a replicated signal, wherein the replicated signal includes a second fundamental component that accurately replicates the first fundamental component; and
a first signal matching circuit configured to modify the second intermediate signal such that the second intermediate signal accurately replicates the first intermediate signal.

21. The communication circuit of claim 20 , further comprising:
a capacitance matching circuit configured to vary a first capacitance such that a second capacitance in a signal path in the amplification circuit maintains a constant ratio relative to a second capacitance in a signal path in the replicator circuit.

22. The communication circuit of claim 20 , wherein the amplified signal is a first current, and wherein the replicated signal is a second current.

23. The communication circuit of claim 20 , wherein the amplified signal is a first voltage, and wherein the replicated signal is a second voltage.

24. The communication circuit of claim 21 , wherein the capacitance matching circuit includes multiple varactors, and includes multiple bias circuits configured to control the multiple varactors.

25. The communication circuit of claim 24 , wherein each of the multiple varactors is connected to a different location in the replicator circuit.

26. The communication circuit of claim 20 , further comprising:
a second signal matching circuit configured to modify an additional intermediate signal in the replicator circuit to accurately replicate an additional intermediate signal in the amplification circuit.

27. The communication circuit of claim 20 , wherein a first offset signal for the first signal matching circuit is generated using analog techniques.

28. The communication circuit of claim 20 , wherein a first offset signal for the first signal matching circuit is generated using mixed signal digital-analog techniques.

Assignees

• Rf Micro Devices (Cayman Islands) Ltd
• Qorvo Us Inc

Inventors

• Scott Baker
• Leipold Dirk Robert Walter
• Maxim George

Classifications

• H03H7/1775

  Parallel LC in shunt or branch path (H03H7/1791 takes precedence) · CPC title

• H03H7/09 Primary

  Filters comprising mutual inductance · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H01F27/385

  for reducing harmonics · CPC title

• H03F1/34

  Negative-feedback-circuit arrangements with or without positive feedback (H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence {; for rejection of common mode signals H03F3/45479}) · CPC title