Semi-dual-active-bridge converter system and methods thereof

Patent metadata

Field	Value
Publication number	US-9748853-B1
Application number	US-201615339943-A
Country	US
Kind code	B1
Filing date	Nov 1, 2016
Priority date	Nov 1, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

One example embodiment is a method executed by a microcontroller with a Pulse Width Modulation (PWM) circuit to control a semi-dual-active-bridge (SDAB) converter that includes a first side bridge circuit, a second side bridge circuit and a transformer. The microcontroller determines a current operation mode and a target operation mode of the SDAB converter. The microcontroller determines an optimal ratio and calculates changes of each gating signal that are applied to the first side bridge circuit and the second side bridge circuit respectively.

First claim

What is claimed is:

1. A method executed by a microcontroller to control a semi-dual-active-bridge (SDAB) converter, the method comprising:
providing the microcontroller with a Pulse Width Modulation (PWM) circuit;
providing the SDAB converter in communication with the microcontroller and including a transformer with a primary winding and a secondary winding with a primary-to-secondary turns ratio of 1:n, a first side bridge circuit that connects to the primary winding of the transformer and includes four active switches, and a second side bridge circuit that connects to the secondary winding of the transformer and includes two active switches and two diodes;
calculating, by the microcontroller and based on an input voltage V s and an output voltage V o of the SDAB converter, a converter gain M of the SDAB converter, wherein M=nV o /V s ;
determining, by the microcontroller and based on a phase shift angle Φ between the first side bridge circuit and the second side bridge circuit, a current operation mode for the SDAB converter;
calculating, by the microcontroller, an adjustment φ to be added to the phase shift angle Φ response to a power adjustment command;
determining, by the microcontroller and based on the adjustment, a target operation mode for the SDAB converter;
determining, by the microcontroller and based on the current operation mode and the target operation mode, an optimal ratio x;
calculating, by the microcontroller, changes of each gating signal that are applied to the first side bridge circuit and the second side bridge circuit respectively to generate calculated gating signals, wherein xφ is a phase shift angle to be adjusted during transition on the first side bridge circuit, and (1−x)φ is a phase shift angle to be adjusted during transition on the second side bridge circuit;
sending, by the microcontroller, the calculated gating signals to the PWM circuit to generate modulated gating signals; and
transmitting, by the microcontroller, the modulated gating signals to the first side bridge circuit and the second side bridge circuit respectively.

2. The method of claim 1 , wherein the current operation mode is Mode A that is a buck-boost mode wherein M>1 and Φ>(M−1)π/M, or M<1 and Φ>(1−M)π/2;
wherein the target operation mode is Mode A that is a buck-boost mode wherein M>1 and (Φ+φ)>(M−1)π/M, or M<1 and (Φ+φ)>(1−M)π/2; and
wherein x=2/(2+M).

3. The method of claim 1 , wherein the current operation mode is Mode B that is a buck mode wherein M<1 and 0<Φ<(1−M)π/2;
wherein the target operation mode is Mode B that is a buck mode wherein M<1 and 0<(Φ+φ)<(1−M)π/2; and
wherein x=2/[(2−M)(1+M)].

4. The method of claim 1 , wherein the current operation mode is Mode C that is a buck mode wherein M<1 and Φ<0;
wherein the target operation mode is Mode C that is a buck mode wherein M<1 and (Φ+φ)<0; and
wherein x=2/(2−M).

5. The method of claim 1 , wherein the current operation mode is Mode B that is a buck mode wherein M<1 and 0<Φ<(1−M)π/2;
wherein the target operation mode is Mode C that is a buck mode wherein M<1 and (Φ+φ)<0, and
wherein x=2/(2−M).

6. The method of claim 1 , wherein the current operation mode is Mode C that is a buck mode wherein M<1 and Φ<0;
wherein the target operation mode is Mode B that is a buck mode wherein M<1 and 0<(Φ+φ)<(1−M)π/2; and
wherein x=2/(2−M).

7. The method of claim 1 , wherein the current operation mode is discontinuous-current mode (DCM) wherein none of conditions (1), (2), and (3) is satisfied in which the conditions are:
(1) M>1 and Φ>(M−1)π/M, or M<1 and Φ>(1−M)π/2;
(2) M<1 and 0<Φ<(1−M)π/2; and
(3) M<1 and Φ<0,
and wherein the target operation mode is DCM wherein none of conditions (a), (b), and (c) is satisfied in which the conditions are:
(a) M>1 and (Φ+φ)>(M−1)π/M, or M<1 and (Φ+φ)>(1−M)π/2;
(b) M<1 and 0<(Φ+φ)<(1−M)π/2; and
(c) M<1 and (Φ+φ)<0.

8. A semi-dual-active-bridge (SDAB) converter system, comprising:
a SDAB converter that includes a transformer having a primary winding and a secondary winding with a primary-to-secondary turns ratio of 1:n, a first side bridge circuit that connects to the primary winding of the transformer and includes four active switches, and a second side bridge circuit that connects to the secondary winding of the transformer and includes two active switches and two diodes; and
a microcontroller that controls the SDAB converter and includes:
a Pulse Width Modulation (PWM) circuit;
a processor; and
a non-transitory computer-readable medium having stored thereon instructions that when executed cause the processor to:
calculate, based on an input voltage V s and an output voltage V o of the SDAB converter, a converter gain M of the SDAB converter, wherein M=nV o /V s ;
determine, based on a phase shift angle Φ between the first side bridge circuit and the second side bridge circuit, a current operation mode for the SDAB converter;
calculate an adjustment φ to be added to the phase shift angle Φ response to a power adjustment command;
determine, based on the adjustment, a target operation mode for the SDAB converter;
determine, based on the current operation mode and the target operation mode, an optimal ratio x;
calculate changes of each gating signal that are applied to the first side bridge circuit and the second side bridge circuit, wherein xφ is a phase shift angle to be adjusted during transition on the first side bridge circuit, and (1−x)φ is a phase shift angle to be adjusted during transition on the second side bridge circuit;
send the calculated gating signals to the PWM circuit to generate modulated gating signals; and
transmit the modulated gating signals to the first side bridge circuit and the second side bridge circuit respectively.

9. The SDAB converter system of claim 8 , wherein the current operation mode is Mode A that is a buck-boost mode wherein M>1 and Φ>(M−1)π/M, or M<1 and Φ>(1−M)π/2;
wherein the target operation mode is Mode A that is a buck-boost mode wherein M>1 and (Φ+φ)>(M−1)π/M, or M<1 and (Φ+φ)>(1−M)π/2; and
wherein x=2/(2+M).

10. The SDAB converter system of claim 8 , wherein the current operation mode is Mode B that is a buck mode wherein M<1 and 0<Φ<(1−M)π/2;
wherein the target operation mode is Mode B that is a buck mode wherein M<1 and 0<(Φ+φ)<(1−M)π/2; and
wherein x=2/[(2−M)(1+M)].

11. The SDAB converter system of claim 8 , wherein the current operation mode is Mode C that is a buck mode wherein M<1 and Φ<0;
wherein the target operation mode is Mode C that is a buck mode wherein M<1 and (Φ+φ)<0; and
wherein x=2/(2−M).

12. The SDAB converter system of claim 8 , wherein the current operation mode is Mode B that is a buck mode wherein M<1 and 0<Φ<(1−M)π/2;
wherein the target operation mode is Mode C that is a buck mode wherein M<1 and (Φ+φ)<0, and
wherein x=2/(2−M).

13. The SDAB converter system of claim 8 , wherein the current operation mode is Mode C that is a buck mode wherein M<1 and Φ<0;
wherein the target operation mode is Mode B that is a buck mode wherein M<1 and 0<(Φ+φ)<(1−M)π/2; and
wherein x=2/(2−M).

14. The SDAB converter system of claim 8 , wherein the current operation mode is discontinuous-current mode (DCM) wherein none of conditions (1), (2), and (3) is satisfied in which the conditions are:
(1) M>1 and Φ>(M−1)π/M, or M<1 and Φ>(1−M)π/2;
(2) M<1 and 0<Φ<(1−M)π/2; and
(3) M<1 and Φ<0,
and wherein the target operation mode is DCM wherein none of conditions (a), (b), and (c) is satisfied in which the conditions are:
(a) M>1 and (Φ+φ)>(M−1)π/M, or M<1 and (Φ+φ)>(1−M)π/2;
(b) M<1 and 0<(Φ+φ)<(1−M)π/2; and
(c) M<1 and (Φ+φ)

Assignees

• Univ Macau Sci & Tech

Inventors

• Li Xiaodong

Classifications

• H02M1/14

  Arrangements for reducing ripples from DC input or output · CPC title

• H02J7/00

  Circuit arrangements for charging or discharging batteries or for supplying loads from batteries · CPC title

• H02M3/33546 Primary

  with automatic control of the output voltage or current (H02M3/33561 takes precedence) · CPC title

• H02J7/0052

  Electricity · mapped topic

• H05B33/0815

  Electricity · mapped topic