Staircase avalanche photodiode with a staircase multiplication region composed of an AIInAsSb alloy

US9748430B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9748430-B2
Application numberUS-201615185914-A
CountryUS
Kind codeB2
Filing dateJun 17, 2016
Priority dateJun 18, 2015
Publication dateAug 29, 2017
Grant dateAug 29, 2017

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Abstract

Official abstract text for this publication.

A staircase avalanche photodiode with a staircase multiplication region composed of an AlInAsSb alloy. The photodiode includes a buffer layer adjacent to a substrate and an avalanche multiplication region adjacent to the buffer layer, where the avalanche multiplication region includes a graded AlInAsSb alloy grown lattice-matched or psuedomorphically strained on either InAs or GaSb. The photodiode further includes a photoabsorption layer adjacent to the avalanche multiplication region, where the photoabsorption layer is utilized for absorbing photons. By utilizing AlInAsSb in the multiplication region, the photodiode exhibits a direct bandgap over a wide range of compositions as well as exhibits large conduction band offsets much larger than the smallest achievable bandgap and small valance band offsets. Furthermore, the photodiode is able to detect extremely weak light with a high signal-to-noise ratio.

First claim

Opening claim text (preview).

The invention claimed is: 1. A photodiode, comprising: an avalanche multiplication region, wherein a combination of all layers of said avalanche multiplication region comprise a graded aluminum indium arsenide antimonide (AlInAsSb) alloy grown lattice-matched or psuedomorphically strained on either indium arsenide (InAs) or gallium antimonide (GaSb), wherein said graded avalanche multiplication region comprises multiple bandgap steps in which a bandgap is varied from small to large and vice-versa; and a photoabsorption layer for absorbing photons. 2. The photodiode as recited in claim 1 further comprising: an InAs or GaSb substrate or an InAs or GaSb buffer. 3. The photodiode as recited in claim 2 , where said avalanche multiplication region is adjacent to said InAs or GaSb substrate or said InAs or GaSb buffer, wherein said photoabsorption layer is adjacent to said avalanche multiplication region. 4. The photodiode as recited in claim 1 , wherein said avalanche multiplication region is directly grown on top of a substrate or a buffer layer, wherein said photoabsorption layer is directly grown on top of said avalanche multiplication region. 5. The photodiode as recited in claim 1 further comprising: a substrate; and a buffer layer adjacent to said substrate. 6. The photodiode as recited in claim 5 , wherein said avalanche multiplication region is positioned on top of said photoabsorption layer, wherein said buffer layer is positioned on top of said avalanche multiplication region, wherein said substrate is positioned on top of said buffer layer. 7. The photodiode as recited in claim 5 , wherein said buffer layer is positioned on top of said substrate, wherein said avalanche multiplication region is positioned on top of said buffer layer, wherein said photoabsorption is positioned on top of said avalanche multiplication region. 8. The photodiode as recited in claim 5 , wherein a thickness of said buffer layer is approximately between 10 nanometers and 10 micrometers. 9. The photodiode as recited in claim 1 further comprising: a contact layer adjacent to said photoabsorption layer. 10. The photodiode as recited in claim 9 , wherein said contact layer comprises gallium antimonide. 11. The photodiode as recited in claim 10 , wherein a thickness of said contact layer is approximately 100 nanometers. 12. The photodiode as recited in claim 1 , wherein said avalanche multiplication region comprises a first layer of indium arsenide antimonide (InAsSb). 13. The photodiode as recited in claim 12 , wherein said first layer has a thickness approximately between 30 nanometers and 1 micrometer. 14. The photodiode as recited in claim 12 , wherein said avalanche multiplication region comprises a second layer of InAsSb, a third layer of aluminum indium arsenide antimonide (AlInAsSb) and a fourth layer of AlInAsSb. 15. The photodiode as recited in claim 14 , wherein said fourth layer is positioned on top of said third layer which is positioned on top said second layer which is positioned on top of said first layer. 16. The photodiode as recited in claim 14 , wherein a thickness of said fourth layer is approximately between 10 nanometers and 2 micrometers. 17. The photodiode as recited in claim 14 , wherein a thickness of said third layer is approximately between 1 nanometer and 100 nanometers. 18. The photodiode as recited in claim 14 , wherein a thickness of said second layer is approximately between 1 nanometer and 100 nanometers. 19. The photodiode as recited in claim 1 , wherein said photoabsorption layer comprises gallium antimonide. 20. The photodiode as recited in claim 19 , wherein a thickness of said photoabsorption layer is approximately between 30 nanometers and 50 micrometers.

Assignees

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Classifications

  • Electricity · mapped topic

  • Electricity · mapped topic

  • having three or more elements, e.g. GaAlAs, InGaAs or InGaAsP · CPC title

  • in which the active layers form heterostructures, e.g. SAM structures · CPC title

  • Solar cells from Group III-V materials · CPC title

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What does patent US9748430B2 cover?
A staircase avalanche photodiode with a staircase multiplication region composed of an AlInAsSb alloy. The photodiode includes a buffer layer adjacent to a substrate and an avalanche multiplication region adjacent to the buffer layer, where the avalanche multiplication region includes a graded AlInAsSb alloy grown lattice-matched or psuedomorphically strained on either InAs or GaSb. The photodi…
Who is the assignee on this patent?
Univ Texas, Univ Virginia Patent Foundation
What technology area does this patent fall under?
Primary CPC classification H01L31/1075. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 29 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).