Method for fabricating a semiconductor device including gate-to-bulk substrate isolation

Patent metadata

Field	Value
Publication number	US-9748404-B1
Application number	US-201615055830-A
Country	US
Kind code	B1
Filing date	Feb 29, 2016
Priority date	Feb 29, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A method for fabricating a semiconductor device comprises forming a sacrificial layer of a first semiconductor material on a substrate, a layer of a second semiconductor material on the sacrificial layer, and a layer of a third semiconductor material on the layer of the second semiconductor material. Portions of the layer of the deposited material are removed to form a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire. An oxidizing process is performed that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
forming a sacrificial layer of a first semiconductor material on a substrate;
forming a layer of a second semiconductor material on the sacrificial layer;
forming a layer of a third semiconductor material on the layer of the second semiconductor material;
removing portions of the layer of the third semiconductor material, portions of the second semiconductor material, and portions of the sacrificial layer to expose portions of the substrate and form a sacrificial fin in the sacrificial layer, a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire;
depositing a layer of insulator material on the substrate adjacent to the sacrificial fin;
etching to remove exposed portions of the first nanowire; and
performing an oxidizing process that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.

2. The method of claim 1 , further comprising forming a gate stack over a channel region of the second nanowire.

3. The method of claim 2 , further comprising removing the first layer of oxide material to expose a portion of the second nanowire prior to forming the gate stack over the channel region of the second nanowire.

4. The method of claim 2 , wherein the gate stack includes a gate dielectric layer arranged on the second nanowire, a work function metal arranged on the gate dielectric layer, and a gate conductor arranged on the work function metal.

5. The method of claim 2 , wherein the forming the gate stack includes depositing a gate dielectric layer over a portion of the second layer of oxide material.

6. The method of claim 1 , wherein the first semiconductor material includes silicon germanium having a first concentration of germanium.

7. The method of claim 6 , wherein the second semiconductor material includes silicon germanium having a second concentration of germanium, wherein the first concentration of germanium is less than the second concentration of germanium.

8. The method of claim 1 , wherein the third semiconductor material includes silicon.

9. The method of claim 1 , wherein the substrate is a bulk semiconductor material.

10. A method for fabricating a semiconductor device, the method comprising:
forming a sacrificial layer of a first semiconductor material on a substrate;
forming a layer of a second semiconductor material on the sacrificial layer;
forming a layer of a third semiconductor material on the layer of the second semiconductor material;
removing portions of the layer of the third semiconductor material, portions of the second semiconductor material, and portions of the sacrificial layer to form a sacrificial fin in the sacrificial layer, a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire;
depositing a layer of insulator material in trenches defined by the sacrificial layer adjacent to the sacrificial fin;
etching to remove exposed portions of the first nanowire; and
performing an oxidizing process that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.

11. The method of claim 10 , further comprising forming a gate stack over a channel region of the second nanowire.

12. The method of claim 11 , further comprising removing the first layer of oxide material to expose a portion of the second nanowire prior to forming the gate stack over the channel region of the second nanowire.

13. The method of claim 11 , wherein the gate stack includes a gate dielectric layer arranged on the second nanowire, a work function metal arranged on the gate dielectric layer, and a gate conductor arranged on the work function metal.

14. The method of claim 11 , wherein the forming the gate stack includes depositing a gate dielectric layer over a portion of the second layer of oxide material.

15. The method of claim 10 , wherein the first semiconductor material includes silicon germanium having a first concentration of germanium.

16. The method of claim 15 , wherein the second semiconductor material includes silicon germanium having a second concentration of germanium, wherein the first concentration of germanium is less than the second concentration of germanium.

17. The method of claim 10 , wherein the third semiconductor material includes silicon.

18. The method of claim 10 , wherein the substrate is a bulk semiconductor material.

Assignees

• IBM

Inventors

• Chang Josephine B
• Guillorn Michael A
• Lauer Isaac
• Miao Xin

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H01L29/42392

  Electricity · mapped topic

• H01L29/78654

  Electricity · mapped topic

• H01L29/66772

  Electricity · mapped topic