Semiconductor device and display device comprising an oxide semiconductor channel region having a different crystal orientation than source/drain regions

Patent metadata

Field	Value
Publication number	US-9748399-B2
Application number	US-201414246493-A
Country	US
Kind code	B2
Filing date	Apr 7, 2014
Priority date	Apr 11, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

To provide a novel semiconductor device in which a reduction in channel length is controlled. The semiconductor device includes an oxide semiconductor layer having a crystal part, and a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a channel formation region and an n-type region in contact with the source electrode layer or the drain electrode layer. The crystal orientation of the crystal part is different between the channel formation region and the n-type region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
a first insulating layer and a second insulating layer over the gate insulating layer;
an oxide semiconductor layer over the gate insulating layer, the first insulating layer, and the second insulating layer, the oxide semiconductor layer including a channel formation region and a pair of n-type regions;
a source electrode layer over the first insulating layer and the oxide semiconductor layer; and
a drain electrode layer over the second insulating layer and the oxide semiconductor layer,
wherein the channel formation region is in contact with the gate insulating layer,
wherein one of the pair of n-type regions is in contact with a top surface and a side surface of the first insulating layer,
wherein the other of the pair of n-type regions is in contact with a top surface and a side surface of the second insulating layer,
wherein a plane where the gate insulating layer is in contact with the oxide semiconductor layer crosses a plane where the first insulating layer is in contact with the oxide semiconductor layer and a plane where the second insulating layer is in contact with the oxide semiconductor layer, and
wherein the oxide semiconductor layer is thinner than the first insulating layer and the second insulating layer.

2. The semiconductor device according to claim 1 ,
wherein a crystal orientation of a crystal part in the channel formation region is different from that of the one of the pair of n-type regions, and
wherein the crystal orientation of the crystal part in the channel formation region is different from that of the other of the pair of n-type regions.

3. The semiconductor device according to claim 2 ,
wherein each c-axis of the crystal parts is aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor layer is formed.

4. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer includes In, Zn, and at least one of Al, Ga, Ge, Y, Zr, Sn, La, Ce, and Hf.

5. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer includes In, Zn and Ga.

6. The semiconductor device according to claim 1 ,
wherein a side surface of the source electrode layer is aligned with a side surface of the first insulating layer, and a side surface of the drain electrode layer is aligned with a side surface of the second insulating layer.

7. A display device comprising the semiconductor device according to claim 1 .

8. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate insulating layer over a gate electrode layer;
forming a first insulating layer and a second insulating layer over the gate insulating layer;
forming an oxide semiconductor layer including a crystal part over the gate insulating layer, the first insulating layer, and the second insulating layer; and
forming a source electrode layer over the first insulating layer and the oxide semiconductor layer, and forming a drain electrode layer over the second insulating layer and the oxide semiconductor layer,
wherein the oxide semiconductor layer includes a channel formation region and a pair of n-type regions,
wherein one of the pair of n-type regions is in contact with a top surface and a side surface of the first insulating layer,
wherein the other of the pair of n-type regions is in contact with a top surface and a side surface of the second insulating layer,
wherein the channel formation region is in contact with the gate insulating layer,
wherein a plane where the gate insulating layer is in contact with the oxide semiconductor layer crosses a plane where the first insulating layer is in contact with the oxide semiconductor layer and a plane where the second insulating layer is in contact with the oxide semiconductor layer, and
wherein the oxide semiconductor layer is thinner than the first insulating layer and the second insulating layer.

9. The method for manufacturing a semiconductor device according to claim 8 ,
wherein a side surface of the source electrode layer is aligned with a side surface of the first insulating layer, and a side surface of the drain electrode layer is aligned with a side surface of the second insulating layer.

Assignees

• Koezuka Junichi
• Okazaki Kenichi
• Takahashi Masahiro
• Matsuo Takuya
• Mori Shigeyasu
• Kanzaki Yosuke
• Matsukizono Hiroshi
• Semiconductor Energy Lab
• Sharp Kk

Inventors

• Koezuka Junichi
• Okazaki Kenichi
• Takahashi Masahiro
• Matsuo Takuya
• Mori Shigeyasu
• Kanzaki Yosuke
• Matsukizono Hiroshi

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L29/7869 Primary

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H01L29/045

  Electricity · mapped topic