Trench MOS semiconductor device

Patent metadata

Field	Value
Publication number	US-9748370-B2
Application number	US-201514622822-A
Country	US
Kind code	B2
Filing date	Feb 13, 2015
Priority date	Mar 19, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

To prevent a malfunction of an overcurrent protection circuit without increasing an on-voltage, and to suppress a short circuit capacity, thus further reducing a switching loss, a trench gate IGBT is provided in which is incorporated a sense IGBT connected in parallel to a main IGBT, where only the sense IGBT portion includes a p-type channel region all over in a semiconductor substrate between adjacent parallel striped trenches, so that the capacitance of the MOS gate of the sense IGBT is smaller than the capacitance of the MOS gate of the main IGBT.

First claim

What is claimed is:

1. A trench MOS semiconductor device, comprising:
a first conductivity type semiconductor substrate, the first conductivity type semiconductor substrate provided with at least a first surface side, and two semiconductor element portions including:
a main semiconductor element portion formed on the semiconductor substrate; and
a current detection sense semiconductor element portion, connected in parallel to the main semiconductor element portion, and having an area, in a plan view, smaller than an area of the main semiconductor element, each of the two semiconductor element portions including:
second conductivity type channel regions formed on the first surface side of the first conductivity type semiconductor substrate and having front surface layers;
first conductivity type emitter regions provided in the front surface layers of the second conductivity type channel regions;
trenches, arranged in a parallel stripe pattern in plan view on the first surface side of the first conductivity type semiconductor substrate, the trenches having a depth greater than the second conductivity type channel regions, the trenches contacting the first conductivity type emitter regions;
conductors filling the trenches via insulating films;
interlayer insulating films covering the conductors; and
a MOS gate structure including a main electrode in common contact with the front surfaces of the second conductivity type channel regions and the first conductivity type emitter regions,

wherein the main semiconductor element portion includes a plurality of unit cells laid out in a checkered pattern in plan view such that in a longitudinal direction between adjacent trenches, adjacent unit cells are separated by the first conductivity-type semiconductor substrate, and such that in a width direction perpendicular to the longitudinal direction in the plan view, adjacent unit cells are separated by the first conductivity-type semiconductor substrate and by adjacent trenches sandwiching the first conductivity-type semiconductor substrate, and such that one unit cell is disposed diagonally to another adjacent unit cell, and
wherein the current detection sense semiconductor element portion has a second conductivity type second channel region extending an entire width of the first surface of the semiconductor substrate between adjacent trenches, and extending an entire length of the first surface of the semiconductor substrate between adjacent unit cells in a longitudinal direction perpendicular to the width direction.

2. The trench MOS semiconductor device according to claim 1 , a density of the unit cells of the sense semiconductor element portion is greater than a density of the unit cells of the main semiconductor element portion, such that a space between the unit cells of the sense semiconductor element is less than a space between the unit cells of the main semiconductor element.

3. The trench MOS semiconductor device according to claim 2 , wherein an area ratio of the area, in the plan view, of the main semiconductor element portion to the area, in the plan view, of the sense semiconductor element portion is 100 to 10000:1.

4. The trench MOS semiconductor device according to claim 1 , wherein an area ratio of the area, in the plan view, of the main semiconductor element portion to the area, in the plan view, of the sense semiconductor element portion is 100 to 10000:1.

5. The trench MOS semiconductor device according to claim 1 , comprising:
a second conductivity type first well region connected to an emitter electrode of the main semiconductor element portion; and
a second conductivity type second well region connected to an emitter electrode of the sense semiconductor element portion, so that the second well region surrounds the sense semiconductor element portion region.

6. The trench MOS semiconductor device according to claim 1 , further comprising:
a space portion provided so that the main semiconductor element portion and the sense semiconductor element portion are spaced from each other, wherein
the semiconductor substrate is exposed to a portion of the space portion on the first surface side of the semiconductor substrate.

7. The trench MOS semiconductor device according to claim 6 , wherein the length of the spaced portion is equal to or more than 25 μm and equal to or less than 30 μm.

8. The trench MOS semiconductor device according to claim 1 , wherein the trench MOS semiconductor device is a field effect transistor.

9. The trench MOS semiconductor device according to claim 1 , wherein the trench MOS semiconductor device is an insulated gate bipolar transistor.

10. A trench MOS semiconductor device, comprising:
a semiconductor substrate, the semiconductor substrate provided with at least a first surface side and two semiconductor element portions including:
a main semiconductor element portion formed on the semiconductor substrate; and
a current detection sense semiconductor element portion, connected in parallel to the main semiconductor element portion, and having an area, in a plan view, smaller than an area of the main semiconductor element,

each of the two semiconductor element portions including:
channel regions formed on the semiconductor substrate;
emitter regions provided in the channel regions;
trenches, arranged in a parallel stripe pattern in plan view on the semiconductor substrate, which extend from the semiconductor substrate, the trenches having a depth greater than the channel regions, the trenches contacting the emitter regions;
conductors filling the trenches via insulating films;
interlayer insulating films covering the conductors; and
a MOS gate structure including a main electrode in common contact with the channel regions and the emitter regions,
wherein the main semiconductor element portion includes a plurality of unit cells laid out in a checkered pattern in plan view such that, in a longitudinal direction between adjacent trenches, adjacent unit cells are separated by the semiconductor substrate, and such that in a width direction perpendicular to the longitudinal direction in the plan view, adjacent unit cells are separated by the semiconductor substrate and by adjacent trenches sandwiching the semiconductor substrate, and such that one unit cell is disposed diagonally to another adjacent unit cell, and
wherein the current detection sense semiconductor element portion has a second channel region extending an entire width of the first surface of the semiconductor substrate between adjacent trenches, and extending an entire length of the first surface of the semiconductor substrate between adjacent unit cells in a longitudinal direction perpendicular to the width direction.

Assignees

• Fuji Electric Co Ltd

Inventors

• Kumada Keishirou

Classifications

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H01L29/0696

  Electricity · mapped topic

• H01L29/402

  Electricity · mapped topic

• H01L29/7397 Primary

  Electricity · mapped topic

• H01L29/0619

  Electricity · mapped topic