Gap fill of metal stack in replacement gate process

Patent metadata

Field	Value
Publication number	US-9748358-B2
Application number	US-201514973780-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
forming a replacement gate structure on a semiconductor layer of a substrate, the replacement gate structure at least comprising a polysilicon layer;
after forming the replacement gate structure, forming a gate spacer on the replacement gate structure;
implanting atoms in an upper portion of the polysilicon layer, the implanting expanding the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the gate spacer, respectively;
after the implanting, removing the polysilicon layer to form a gate cavity surrounded by the gate spacer; and
forming a metal gate stack within the gate cavity and in contact with sidewalls of the gate spacer, the metal gate stack comprising a upper portion having a width that is greater than a width of a lower portion of the metal gate stack.

2. The method of claim 1 , wherein the atoms are germanium atoms and are implanted at a dose that is greater than 10 15 Ge atoms/cm 2 .

3. The method of claim 1 , wherein forming the replacement gate structure comprises:
forming a dielectric layer on the semiconductor layer; and
forming the polysilicon layer on and in contact with the dielectric layer.

4. The method of claim 1 , further comprising:
forming a source region and a source extension region within the semiconductor layer;
forming a drain region and a drain extension region within the semiconductor layer; and
forming silicide areas in the source and drain regions.

5. The method of claim 4 , further comprising:
forming a protective liner over the silicide areas, the gate spacer, and the replacement gate structure; and
forming a dielectric layer over and in contact with the protective liner.

6. The method of claim 1 , wherein forming the metal gate stack comprises:
depositing a dielectric material within the gate cavity to form a gate dielectric layer conforming to sidewalls of the gate spacer; and
depositing one or more conductive materials on the gate dielectric layer to form a metal gate.

7. The method of claim 1 , further comprising:
defining an active area within the semiconductor layer.

8. The method of claim 1 , further comprising:
forming isolation regions within the semiconductor layer.

9. The method of claim 4 , wherein forming the silicide areas in the source and drain regions comprises:
depositing a metal in contact with the source and drain regions;
performing an anneal, the anneal forming the silicide areas from the metal; and
selectively removing unreacted metal after the anneal.

10. The method of claim 4 , further comprising:
forming a disposable material layer over at the silicide areas, the disposable material layer protecting the silicide areas from the implanting.

11. The method of claim 10 , further comprising:
removing the disposable material layer after the implanting.

12. The method of claim 1 , further comprising:
removing a hard mask of the replacement gate prior to the implanting.

13. The method of claim 5 , further comprising:
etching the protective liner and the dielectric layer down to a top surface of the gate spacer.

14. The method of claim 1 , wherein forming the metal gate stack comprises:
forming in contact with a dielectric layer within the gate cavity remaining from the replacement gate structure.

15. A method for fabricating a semiconductor device, the method comprising:
forming a replacement gate structure on a semiconductor layer of a substrate, the replacement gate structure at least comprising a polysilicon layer;
after forming the replacement gate structure, forming a gate spacer on the replacement gate structure;
implanting atoms in an upper portion of the polysilicon layer, the implanting expanding the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the gate spacer, respectively;
after the implanting, removing the polysilicon layer to form a gate cavity surrounded by the gate spacer;
depositing a dielectric material within the gate cavity to form a gate dielectric layer conforming to sidewalls of the gate spacer;
depositing a work function metal in contact with the dielectric material; and
depositing a conductive material in contact with the work function metal, the dielectric material, work function metal, and conductive material forming a metal gate.

16. The method of claim 15 , wherein the atoms are germanium atoms and are implanted at a dose that is greater than 10 15 Ge atoms/cm 2 .

17. The method of claim 15 , wherein forming the replacement gate structure comprises:
forming a dielectric layer on the semiconductor layer; and
forming the polysilicon layer on and in contact with the dielectric layer.

18. The method of claim 15 , further comprising:
forming a source region and a source extension region within the semiconductor layer;
forming a drain region and a drain extension region within the semiconductor layer; and
forming silicide areas in the source and drain regions.

19. The method of claim 18 , further comprising:
forming a protective liner over the silicide areas, the gate spacer, and the replacement gate structure; and
forming a dielectric layer over and in contact with the protective liner.

20. The method of claim 15 , wherein forming the metal gate stack comprises:
depositing a dielectric material within the gate cavity to form a gate dielectric layer conforming to sidewalls of the gate spacer; and
depositing one or more conductive materials on the gate dielectric layer to form a metal gate.

Assignees

• IBM

Inventors

• Chan Victor
• Han Jin Ping
• KO Shangbin

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L21/283

  Electricity · mapped topic