Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9748312-B2
Application number	US-201615072748-A
Country	US
Kind code	B2
Filing date	Mar 17, 2016
Priority date	Oct 29, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

According to an embodiment, a semiconductor memory device comprises: a first semiconductor layer extending in a first direction; a first wiring line extending in a second direction intersecting the first direction; a variable resistance layer provided between these first wiring line and first semiconductor layer; and a first gate electrode extending in the first direction and facing the first semiconductor layer via a first insulating layer. In addition, this semiconductor memory device comprises a second gate electrode provided in the first direction with respect to the first wiring line, extending in the second direction in parallel to the first wiring line, and facing the first semiconductor layer. This second gate electrode faces the first semiconductor layer via a second insulating layer. Moreover, this second gate electrode faces the first gate electrode via the second insulating layer, the first semiconductor layer, and the first insulating layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a first semiconductor layer extending in a first direction;
a first wiring line extending in a second direction intersecting the first direction;
a variable resistance layer provided between the first wiring line and the first semiconductor layer;
a first gate electrode extending in the first direction and facing the first semiconductor layer via a first insulating layer; and
a second gate electrode provided in the first direction with respect to the first wiring line, extending in the second direction in parallel to the first wiring line, and facing the first semiconductor layer,
the second gate electrode facing the first semiconductor layer via a second insulating layer, and facing the first gate electrode via the second insulating layer, the first semiconductor layer, and the first insulating layer.

2. The semiconductor memory device according to claim 1 , wherein
one end in the first direction of the first gate electrode is positioned between one end in the first direction and another end on an opposite side in the first direction, of the second gate electrode.

3. The semiconductor memory device according to claim 1 , wherein
the first direction is a direction crossing a substrate, and
a lower end on a substrate side of the first gate electrode is positioned more downwardly than an upper surface of the second gate electrode.

4. The semiconductor memory device according to claim 1 , wherein
the second gate electrode is formed in a comb shape.

5. The semiconductor memory device according to claim 3 , further comprising
a second semiconductor layer connected to a lower end portion of the first semiconductor layer,
wherein an impurity concentration in the second semiconductor layer is higher than an impurity concentration in the first semiconductor layer,
the second semiconductor layer covers a side surface and lower surface of the lower end portion of the first semiconductor layer, and
second insulating layer is provided on a side surface of the second semiconductor layer.

6. The semiconductor memory device according to claim 1 , further comprising
a plurality of the first wiring lines arranged in the first direction,
wherein the first semiconductor layer comprises: a first facing portion facing the first wiring line; and a second facing portion facing an inter-layer insulating layer provided between the first wiring lines, and
the first facing portion projects with respect to the second facing portion.

7. The semiconductor memory device according to claim 6 , wherein
the first facing portion projects 1 nm or more with respect to the second facing portion.

8. The semiconductor memory device according to claim 6 , wherein
a surface facing the first semiconductor layer of the first wiring line is recessed with respect to a surface facing the first semiconductor layer of the inter-layer insulating layer, and
the first semiconductor layer, the first insulating layer, and the first gate electrode are formed concavely-and-convexly along side surfaces of the first wiring line and the inter-layer insulating layer.

9. The semiconductor memory device according to claim 1 , wherein
a distance between the first semiconductor layer and a central position in the first direction of the first wiring line is shorter than a distance between the first semiconductor layer and positions of both ends in the first direction of the first wiring line.

10. The semiconductor memory device according to claim 1 , further comprising
a plurality of the first wiring lines arranged in the first direction,
wherein the variable resistance layer is provided commonly between a plurality of the first wiring lines and the first semiconductor layer.

11. The semiconductor memory device according to claim 1 , further comprising:
a plurality of the first wiring lines arranged in the first direction; and
a plurality of the variable resistance layers arranged in the first direction, wherein
the plurality of variable resistance layers are respectively provided between the first wiring lines and the first semiconductor layer.

12. A semiconductor memory device, comprising:
a first semiconductor layer extending in a first direction;
a plurality of first wiring lines arranged in the first direction and extending in a second direction intersecting the first direction;
a variable resistance layer provided between the first wiring line and the first semiconductor layer; and
a first gate electrode extending in the first direction and facing the first semiconductor layer via a first insulating layer,
the first semiconductor layer comprising: a first facing portion facing the first wiring line; and a second facing portion facing an inter-layer insulating layer provided between the first wiring lines, and
the first facing portion projecting with respect to the second facing portion.

13. The semiconductor memory device according to claim 12 , further comprising
a second gate electrode provided in the first direction with respect to the first wiring line, extending in the second direction in parallel to the first wiring line, and facing the first semiconductor layer,
wherein one end in the first direction of the first gate electrode is positioned between one end in the first direction and another end on an opposite side in the first direction, of the second gate electrode.

14. The semiconductor memory device according to claim 12 , wherein
the first direction is a direction crossing a substrate,
the semiconductor memory device further comprises a second gate electrode provided on a substrate side with respect to the first wiring line, extending in the second direction in parallel to the first wiring line, and facing the first semiconductor layer, and
a lower end on a substrate side of the first gate electrode is positioned more downwardly than an upper surface of the second gate electrode.

15. The semiconductor memory device according to claim 12 , further comprising
a second gate electrode provided in the first direction with respect to the first wiring line, extending in the second direction in parallel to the first wiring line, and facing the first semiconductor layer,
wherein the second gate electrode is formed in a comb shape.

16. The semiconductor memory device according to claim 12 , wherein
the first facing portion projects 1 nm or more with respect to the second facing portion.

17. The semiconductor memory device according to claim 12 , wherein
a surface facing the first semiconductor layer of the first wiring line is recessed with respect to a surface facing the first semiconductor layer of the inter-layer insulating layer, and
the first semiconductor layer, the first insulating layer, and the first gate electrode are formed concavely-and-convexly along side surfaces of the first wiring line and the inter-layer insulating layer.

18. The semiconductor memory device according to claim 12 , wherein
a distance between the first semiconductor layer and a central position in the first direction of the first wiring line is shorter than a distance between the first semiconductor layer and positions of both ends in the first direction of the first wiring line.

19. The semiconductor memory device according to claim 12 , further comprising:
a plurality of variable resistance layers arranged in the first direction, and
the plurality of variable resistance layers are respectively provided between the first wiring lines and the first semiconductor layer.

Assignees

• Toshiba Kk

Inventors

• Izumida Takashi
• Tajima Hikari

Classifications

• H01L45/085

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H01L27/249 Primary

  Electricity · mapped topic

• H01L29/42376

  Electricity · mapped topic

• H01L27/2436

  Electricity · mapped topic