System and method of manufacturing a thin film transistor substrate

Patent metadata

Field	Value
Publication number	US-9748283-B2
Application number	US-201514664232-A
Country	US
Kind code	B2
Filing date	Mar 20, 2015
Priority date	Oct 6, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

In a method of manufacturing a thin film transistor substrate, a first metal layer is formed on a first surface of a base substrate. The base substrate is cooled by contacting the first metal layer with a first cooling plate and by contacting a second surface of the base substrate with a second cooling plate. The first and second surfaces of the base substrate face opposite directions. A gate electrode is formed by patterning the first metal layer. A source electrode and a drain electrode are formed. The source electrode is spaced apart from the drain electrode. The source and drain electrodes partially overlap the gate electrode. A pixel electrode electrically connected to the drain electrode is formed.

First claim

What is claimed is:

1. A method of manufacturing a thin film transistor substrate, the method comprising:
forming a first metal layer on a first surface of a base substrate;
cooling the base substrate by directly contacting the first metal layer with at least the central portion of a first cooling plate and by directly contacting a second surface of the base substrate with at least the central portion of a second cooling plate, the first and second surfaces of the base substrate facing opposite directions;
forming a gate electrode by patterning the first metal layer;
forming a source electrode and a drain electrode, the source electrode being spaced apart from the drain electrode, the source and drain electrodes partially overlapping the gate electrode; and
forming a pixel electrode electrically connected to the drain electrode.

2. The method of claim 1 , wherein the first metal layer includes at least one conductive material selected from the group consisting of aurum (Au), copper (Cu), nickel (Ni), aluminum (Al), molybdenum (Mo), chrome (Cr), tantalum (Ta), titanium (Ti) and an alloy thereof.

3. The method of claim 1 , wherein the first metal layer has a thickness of about 1 μm to about 3 μm.

4. The method of claim 1 , wherein the base substrate is cooled to a temperature of about −60° C. to about 0° C.

5. The method of claim 1 , wherein forming the gate electrode includes preheating the cooled base substrate before patterning the first metal layer.

6. The method of claim 5 , wherein the base substrate is preheated to the ambient temperature.

7. The method of claim 1 , wherein forming the source electrode and the drain electrode includes:
forming a second metal layer on the base substrate on which the gate electrode is formed;
cooling the base substrate by contacting the second metal layer with the first cooling plate and by contacting the second surface of the base substrate with the second cooling plate; and
patterning the second metal layer.

8. The method of claim 7 , wherein the second metal layer includes at least one conductive material selected from the group consisting of aurum (Au), copper (Cu), nickel (Ni), aluminum (Al), molybdenum (Mo), chrome (Cr), tantalum (Ta), titanium (Ti) and an alloy thereof.

9. The method of claim 1 , wherein forming the pixel electrode includes:
forming a third metal layer on the base substrate on which the source and drain electrodes are formed;
cooling the base substrate by contacting the third metal layer with the first cooling plate and by contacting the second surface of the base substrate with the second cooling plate; and
patterning the third metal layer.

10. The method of claim 9 , wherein the third metal layer includes at least one conductive material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO) and aluminum zinc oxide (AZO).

Assignees

• Samsung Display Co Ltd

Inventors

• Yang Su-Kyoung
• Shin Sang-Won
• Shin Hyun-Eok
• Yang Chan-Woo
• Lee Dong-Min

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H01L29/45

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L29/42372

  Electricity · mapped topic

• H01L27/1259 Primary

  Electricity · mapped topic