Semiconductor device having contact plugs and method of forming the same

Patent metadata

Field	Value
Publication number	US-9748243-B2
Application number	US-201615049721-A
Country	US
Kind code	B2
Filing date	Feb 22, 2016
Priority date	Apr 21, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A semiconductor device including a first fin active area substantially parallel to a second fin active area, a first source/drain in the first fin active area, a second source/drain in the second fin active area, a first contact plug on the first source/drain, and a second contact plug on the second source/drain. The center of the second contact plug is offset from the center of the second source/drain.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first fin active area;
a second fin active area substantially parallel to the first fin active area;
a first source/drain in the first fin active area;
a second source/drain in the second fin active area;
a first contact plug on the first source/drain; and
a second contact plug on the second source/drain, wherein the second contact plug is only on one source/drain corresponding to the second source/drain and wherein a center of the second contact plug is offset from a center of the second source/drain.

2. The semiconductor device as claimed in claim 1 , wherein a bottom of the second contact plug has a different inclination from a bottom of the first contact plug.

3. The semiconductor device as claimed in claim 1 , further comprising:
an inclined interface between the second contact plug and the second source/drain, the inclined interface at a higher level in a direction approaching the first fin active area and at a lower level in a direction away from the first fin active area.

4. The semiconductor device as claimed in claim 1 , wherein a distance between a vertical center of the first contact plug and a vertical center of the second contact plug is greater than a distance between a vertical center of the first source/drain and a vertical center of the second source/drain.

5. The semiconductor device as claimed in claim 1 , wherein a lower end of the second contact plug is at a lower level than a lower end of the first contact plug.

6. The semiconductor device as claimed in claim 1 , wherein:
a horizontal width of the first source/drain is greater than a horizontal width of the first fin active area, and
a horizontal width of the second source/drain is greater than a horizontal width of the second fin active area.

7. The semiconductor device as claimed in claim 1 , wherein a farthest point of an interface between the second contact plug and the second source/drain from a vertical line passing through a center of the first source/drain is at a lower level than a closest point of the interface between the second contact plug and the second source/drain to the vertical line passing through the center of the first source/drain.

8. The semiconductor device as claimed in claim 1 , further comprising:
a third fin active area substantially parallel to the second fin active area;
a third source/drain in the third fin active area; and
a third contact plug on the third source/drain, wherein the second fin active area is between the first fin active area and the third fin active area, and wherein a center of the third contact plug is offset from a center of the third source/drain.

9. A semiconductor device, comprising:
first and second pull-up transistors;
first and second pull-down transistors;
first and second access transistors;
a first contact plug adjacent to the second pull-up transistor; and
a second contact plug adjacent to the second pull-down transistor, wherein a first source/drain in a first fin active area of the second pull-up transistor is connected to the first contact plug, a second source/drain in a second fin active area of the second pull-down transistor is connected to the second contact plug, and a center of the second contact plug is offset from a center of the second source/drain.

10. The semiconductor device as claimed in claim 9 , wherein the second fin active area is substantially parallel to the first fin active area.

11. The semiconductor device as claimed in claim 9 , wherein:
the first source/drain includes P-type impurities, and
the second source/drain includes N-type impurities.

12. The semiconductor device as claimed in claim 9 , wherein:
the first source/drain includes a crystal-growth SiGe layer, and
the second source/drain includes a crystal-growth Si layer, a crystal-growth SiC layer, or a combination thereof.

13. The semiconductor device as claimed in claim 9 , a distance between a vertical center of the first contact plug and a vertical center of the second contact plug is greater than a distance between a vertical center of the first source/drain and a vertical center of the second source/drain.

14. The semiconductor device as claimed in claim 9 , further comprising:
a third contact plug adjacent to the first pull-down transistor,
wherein a third source/drain in a third fin active area of the first pull-down transistor is connected to the third contact plug, and a center of the third contact plug is offset from a center of the third source/drain.

15. A semiconductor device, comprising:
a first source/drain area;
a second source/drain area;
a first contact plug on the first source/drain area; and
a second contact plug on the second source/drain area, wherein a center of the second contact plug is offset from a center of the second source/drain, wherein a farthest point of an interface between the second contact plug and the second source/drain area from a vertical line passing through the center of the first source/drain area is at a lower level than a closest point of the interface between the second contact plug and the second source/drain area to the vertical line passing through the center of the first source/drain area.

16. The semiconductor device as claimed in claim 15 , wherein the first contact plug is adjacent the second contact plug.

17. The semiconductor device as claimed in claim 15 , wherein:
the center of the first contact plug is spaced from the center of the second contact plug by a first distance;
the center of the first source/drain area is spaced from the center of the second source/drain area by a second distance; and
the first distance is greater than the second distance.

18. The semiconductor device as claimed in claim 15 , wherein a lower surface of the second contact plug is inclined.

19. The semiconductor device as claimed in claim 15 , wherein:
a lower surface of the first contact plug has a first shape;
a lower surface of the second contact plug has a second shape; and
the first shape is different from the second shape.

20. The semiconductor device as claimed in claim 15 , further comprising:
a third source/drain area; and
a third contact plug on the third source/drain area,
wherein the second source/drain area is between the first source/drain area and the third source/drain area, and a center of the third contact plug is offset from a center of the third source/drain area.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Changseop
• Kim Sungmin
• Cho Chiwon

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H01L27/0886

  Electricity · mapped topic