Semiconductor device

Patent metadata

Field	Value
Publication number	US-9748229-B2
Application number	US-201514954867-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Aug 28, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n + emitter region and an n − drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n + emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a floating region of a first conductivity type selectively in a semiconductor substrate of a second conductivity type and a trench in the semiconductor substrate at a position bordering the floating region;
forming an insulating film on a surface of the semiconductor substrate and on inner surfaces of the trench;
thereafter, forming a conductive layer on the surface of the semiconductor substrate and on the inner surfaces of the trench having the insulating film thereon;
performing anisotropic etching on the conductive layer to pattern the conductive layer such that, in the trench, the patterned conductive layer provides an emitter connecting part on one inner surface of the trench at a side facing the floating region and a trench gate on another inner surface of the trench at a side opposite thereto, the emitter connecting part and the trench gate being separated from each other by a gap;
forming a center insulating film that separates and insulates the emitter connecting part from the trench gate in the trench;
forming an emitter region of the second conductivity type in the surface of the semiconductor substrate and a base region of the first conductivity type under the emitting region at a side of the trench opposite to the floating region;
thereafter, forming an interlayer insulating film on the surface of the semiconductor substrate;
forming a contact trench that extends vertically downwardly and penetrates through the interlayer insulating film and the emitter region, thereby reaching an inside of the base region thereunder;
forming a base contact region of the first conductivity type in the inside of the base region that has been exposed by the contact trench;
forming an emitter electrode on the surface of the semiconductor substrate so that the emitter electrode contacts the emitter region, the base region, and the base contact region through the contact trench; and
forming a collector region of the first conductivity type on a rear surface of the semiconductor substrate,
wherein the forming of the floating region and the trench includes:
selectively doping the surface of the semiconductor substrate with impurities of the first conductivity type to form a doped region in the semiconductor substrate;
forming the trench at a position bordering the doped region;
oxidizing the surface of the semiconductor substrate having the trench therein to form a sacrificial oxide film on said surface and on the inner surfaces of the trench;
annealing the semiconductor substrate having the sacrificial oxide film formed thereon to diffuse the impurities of the first conductive type into the semiconductor substrate so as to form the floating region of the first conductivity type in the semiconductor substrate; and
removing the sacrificial oxide layer.

2. The method according to claim 1 , wherein the forming of the center insulating film includes:
forming an insulating layer on the surface of the semiconductor substrate including the trench, thereby filling the gap between the emitter connecting part and the trench gate in the trench; and
performing etch-back on the insulating layer so that a surface thereof is substantially leveled with the surface of the semiconductor substrate to leave the center insulating film in the trench.

3. The method according to claim 1 , wherein
the forming of the floating region and the trench also includes forming a second trench in the semiconductor layer, said second trench reaching at least the floating region and having a same width as the trench;
the performing of the anisotropic etching includes patterning the conductive layer such that, in the second trench, the patterned conductive layer provides a pair of second emitter connecting parts that are insulated from each other in the second trench by a gap; and
the forming of the center insulating film includes forming an insulating film that separates and insulate the pair of second emitter connecting parts in the second trench.

Assignees

• Rohm Co Ltd

Inventors

• Hikasa Akihiro

Classifications

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H01L29/7397

  Electricity · mapped topic

• H01L29/0619

  Electricity · mapped topic

• H01L29/0804

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic