Structure and method for cooling three-dimensional integrated circuits

Patent metadata

Field	Value
Publication number	US-9748228-B2
Application number	US-201314014532-A
Country	US
Kind code	B2
Filing date	Aug 30, 2013
Priority date	Aug 30, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

First claim

It is claimed:

1. An apparatus comprising:
a three-dimensional integrated circuit (3DIC) comprising multiple device layers stacked vertically over a substrate;
a cooling element thermally connected to the 3DIC and including a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC, each of the cooling modules including:
a cold pole configured to absorb heat from the 3DIC, and
a heat sink configured to dissipate the heat absorbed by the cold pole, the heat sink (i) being coupled to the cold pole via N- and P-type semiconductor elements that are stacked vertically over the substrate, and (ii) including portions that are disposed over a top device layer of the 3DIC and disposed below a bottom device layer of the 3DIC; and

a temperature sensing structure configured to measure temperatures at a second plurality of locations relative to the 3DIC, wherein the measured temperatures control the plurality of cooling modules.

2. The apparatus of claim 1 ,
wherein each of the device layers i) includes a semiconductor device, and ii) is separated from other device layers by an interface, and
wherein the plurality of individually controllable cooling modules are arranged in an array structure.

3. The apparatus of claim 2 ,
wherein the plurality of device layers include a plurality of circuit blocks, and
wherein the plurality of individually controllable cooling elements arranged in the array structure are configured to be turned on and off on an individual basis based on temperatures measured within the plurality of circuit blocks.

4. The apparatus of claim 2 , wherein the cooling element includes portions integrated within the plurality of device layers, and wherein for each of the cooling modules:
the cold pole includes a portion that is located at the interface between the device layers, and
the N-type semiconductor element and the P-type semiconductor element are separated vertically by the cold pole.

5. The apparatus of claim 4 , wherein the plurality of device layers includes i) a first device layer, and ii) a second device layer stacked vertically over the first device layer, and wherein for each of the cooling modules:
the cold pole comprises a first metal structure;
a portion of the heat sink disposed over the second device layer comprises a second metal structure; and
a portion of the heat sink disposed beneath the first device layer comprises a third metal structure.

6. The apparatus of claim 4 , wherein the plurality of device layers includes i) a first device layer, and ii) a second device layer stacked vertically over the first device layer, and wherein for each of the cooling modules:
the cold pole includes:
a first metal structure located at the interface between the first device layer and the second device layer,
a second metal structure disposed over the second device layer,
a third metal structure disposed beneath the first device layer, and
first and second through silicon vias that couple the first metal structure with each of the second and the third metal structures;

the N-type semiconductor element is disposed over the second device layer or beneath the first device layer, wherein the N-type semiconductor element is configured to couple the second metal structure or the third metal structure to the heat sink; and
the P-type semiconductor element is disposed over the second device layer or beneath the first device layer, wherein the P-type semiconductor element is configured to couple the second metal structure or the third metal structure to the heat sink.

7. The apparatus of claim 5 , wherein the plurality of device layers includes i) a first device layer, and ii) a second device layer stacked vertically over the first device layer, and wherein for each of the cooling modules:
the cold pole includes:
a first metal structure located at the interface between the first device layer and the second device layer,
a second metal structure disposed over the second device layer, and
a through silicon via that couples the first metal structure with the second metal structure;

an inter metal layer is disposed between the cold pole and a portion of the heat sink disposed beneath the first device layer; and
the N-type semiconductor element or the P-type semiconductor element is disposed over the second device layer and couples the second metal structure with a portion of the heat sink disposed over the second device layer.

8. The apparatus of claim 4 , wherein the plurality of device layers includes i) a first device layer, and ii) a second device layer stacked vertically over the first device layer, and wherein for each of the cooling modules:
the cold pole includes:
a first metal structure located at the interface between the first device layer and the second device layer,
a second metal structure disposed beneath the first device layer, and
a through silicon via that couples the first metal structure with the second metal structure;

an inter metal layer is disposed between the cold pole and a portion of the heat sink disposed over the second device layer of the 3DIC;
a first semiconductor layer includes the N-type semiconductor element or the P-type semiconductor element, wherein the first semiconductor layer is disposed beneath the first device layer and couples the second metal structure with a portion of the heat sink disposed beneath the first device layer of the 3DIC; and
a second semiconductor layer includes the N-type semiconductor element or the P-type semiconductor element, wherein the second semiconductor element couples the inter metal layer with the portion of the heat sink disposed over the second device layer.

9. The apparatus of claim 4 , wherein the plurality of device layers includes i) a first device layer, and ii) a second device layer stacked vertically over the first device layer, and wherein for each of the cooling modules:
the cold pole includes a first metal structure located at the interface between the first device layer and the second device layer;
a first inter metal layer is disposed between the cold pole and a portion of the heat sink disposed over the second device layer;
a second inter metal layer is disposed between the cold pole and a portion of the heat sink disposed beneath the first device layer of the 3DIC;
a first semiconductor layer includes the N-type semiconductor element or the P-type semiconductor element, wherein the first semiconductor element couples the first inter metal layer with the portion of the heat sink disposed over the second device layer; and
a second semiconductor layer includes the N-type semiconductor element or the P-type semiconductor element, wherein the second semiconductor element couples the first metal structure with the second inter metal layer.

10. The apparatus of claim 1 , wherein the N-type semiconductor element or the P-type semiconductor element includes a superlattice structure, and wherein the superlattice structure is a periodic structure of layers of two or more materials.

11. The apparatus of claim 10 , wherein the N-type semiconductor element includes the superlattice structure, and wherein the two or more materials include InAs, GaSb, Al x Ga 1-x Sb, or Al y Ga 1-y As.

12. The apparatus of claim 10 , wherein the P-type semiconductor element includes the superlattice structure, and wherein the two or more materials include AlGaN, GaN, SiGe, or Si.

13. The apparatus of claim 1 , wherein each of the device layers includes a semiconductor device, and wherein the apparatus further comprises:
a memory, wherein in controlling the plurality of cooling modules vi

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Hui-Yu
• Chang Chi-Wen
• Kuan Jui-Feng
• Cheng Yi-Kan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title