Semiconductor device with power transistors coupled to diodes

Patent metadata

Field	Value
Publication number	US-9748225-B2
Application number	US-201514970627-A
Country	US
Kind code	B2
Filing date	Dec 16, 2015
Priority date	Feb 6, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L 5 ) is laid which functions as a source of a power transistor (Q 3 ) and a cathode of a diode (D 4 ), and further functioning as a drain of a power transistor (Q 4 ) and an anode of a diode (D 3 ). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.

First claim

What is claimed is:

1. A semiconductor device comprising a semiconductor chip, the semiconductor chip comprising:
a first power transistor,
a first diode coupled to the first power transistor in antiparallel,
a second diode coupled to the first power transistor in series, and
a second power transistor coupled to the first diode in series, and further coupled to the second diode in antiparallel;
wherein the first power transistor comprises:
a first drain and a first source that are arranged apart from each other in plan view, and
a first gate electrode that provides ON/OFF control of a current flowing between the first drain and the first source;

wherein the second power transistor comprises:
a second drain and a second source that are arranged apart from each other in plan view, and
a second gate electrode that provides ON/OFF control of a current flowing between the second drain and the second source;

wherein the first diode comprises:
a first cathode coupled electrically to the first drain, and
a first anode coupled electrically to the first source and the second drain;

wherein the second diode comprises:
a second cathode coupled electrically to the first source and the second drain, and
a second anode coupled electrically to the second source,

wherein the semiconductor chip comprises:
a first interconnect functioning as the first drain of the first power transistor and the first cathode of the first diode,
a second interconnect functioning as the first source of the first power transistor and the second cathode of the second diode, and further functioning as the second drain of the second power transistor and the first anode of the first diode, and
a third interconnect functioning as the second source of the second power transistor and the second anode of the second diode,

wherein the first power transistor and the first diode are arranged side by side in a first direction,
wherein the second diode and the second power transistor are arranged side by side in the first direction,
wherein the first power transistor and the second diode are arranged side by side in a second direction crossing the first direction,
wherein the first diode and the second power transistor are arranged side by side in the second direction, and
wherein the first to the third interconnects are extended in the first direction and are apart from each other.

2. The semiconductor device according to claim 1 ,
wherein a plurality of units, each comprising the first power transistor or the second power transistor, the first diode or the second diode, and the first, the second or the third interconnect, are formed in the semiconductor chip.

3. The semiconductor device according to claim 2 ,
wherein paired units of the units are formed in the semiconductor chip, and
wherein the paired units are constituent elements of a full bridge circuit.

4. The semiconductor device according to claim 1 , comprising:
a first wire multipoint-bonded to the first interconnect,
a second wire multipoint-bonded to the second interconnect, and
a third wire multipoint-bonded to the third interconnect.

5. A semiconductor device comprising a semiconductor chip, the semiconductor chip comprising:
a first power transistor,
a first diode coupled to the first power transistor in antiparallel,
a second diode coupled to the first power transistor in series, and
a second power transistor coupled to the first diode in series, and further coupled to the second diode in antiparallel;
wherein the first power transistor comprises:
a first drain and a first source that are arranged apart from each other in plan view, and
a first gate electrode that provides ON/OFF control of a current flowing between the first drain and the first source;

wherein the second power transistor comprises:
a second drain and a second source that are arranged apart from each other in plan view, and
a second gate electrode that provides ON/OFF control of a current flowing between the second drain and the second source;

wherein the first diode comprises:
a first cathode coupled electrically to the first drain, and
a first anode coupled electrically to the first source and the second drain;

wherein the second diode comprises:
a second cathode coupled electrically to the first source and the second drain, and
a second anode coupled electrically to the second source,

wherein the semiconductor chip comprises:
a first interconnect functioning as the first drain of the first power transistor and the first cathode of the first diode,
a second interconnect functioning as the first source of the first power transistor and the second cathode of the second diode, and further functioning as the second drain of the second power transistor and the first anode of the first diode, and
a third interconnect functioning as the second source of the second power transistor and the second anode of the second diode,

wherein the first to the third interconnects are extended in a first direction and are apart from each other,
wherein the first power transistor and the second power transistor each comprise a plurality of unitary transistors coupled to each other in parallel,
wherein each of the unitary transistors comprises a drain electrode and a source electrode extended in a second direction crossing the first direction and are apart from each other in plan view,
wherein the drain electrode of each of the unitary transistors of the first power transistor is electrically coupled to the first interconnect functioning as the first drain,
wherein the source electrode of each of the unitary transistors of the first power transistor is electrically coupled to the second interconnect functioning as the first source,
wherein the drain electrode of each of the unitary transistors of the second power transistor is electrically coupled to the second interconnect functioning as the second drain, and
wherein the source electrode of each of the unitary transistors of the second power transistor is electrically coupled to the third interconnect functioning as the second source.

6. The semiconductor device according to claim 5 ,
wherein the semiconductor chip comprises an electron transit layer and an electron supply layer formed over the electron transit layer,
wherein a square well potential is formed in an interface between the electron transit layer and the electron supply layer, and
wherein the drain electrode and the source electrode of each of the unitary transistors are formed over the electron supply layer and are apart from each other.

7. The semiconductor device according to claim 6 ,
wherein the electron transit layer and the electron supply layer are each a nitride semiconductor layer.

8. The semiconductor device according to claim 5 ,
wherein a plurality of units each comprising the first power transistor or the second power transistor, the first diode or the second diode, and the first, the second or the third interconnect are formed in the semiconductor chip.

9. The semiconductor device according to claim 8 ,
wherein paired units of the units are formed in the semiconductor chip, and
wherein the paired units are constituent elements of a full bridge circuit.

10. The semiconductor device according to claim 5 , comprising:
a first wire multipoint-bonded to the first interconnect,
a second wire multipoint-bonded to the second interconnect, and
a third wire multipoint-bonded to the third interconnect.

11. A semiconductor device comprising a semiconductor chip, the semiconductor chip comprising:
a first power transistor,
a first diode coupled to the first power transistor in antiparallel,
a sec

Assignees

• Renesas Electronics Corp

Inventors

• Miura Yoshinao
• Miyamoto Hironobu
• Okamoto Yasuhiro

Classifications

• H10W72/07552

  changes in structures or sizes · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/5438

  the bond wires having multiple connections on the same bond pad · CPC title