Multi-chip package structure and method of forming same

Patent metadata

Field	Value
Publication number	US-9748189-B2
Application number	US-201414561581-A
Country	US
Kind code	B2
Filing date	Dec 5, 2014
Priority date	Aug 1, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least one V-shaped via and a plurality of bumps formed on and electrically coupled to the interconnect structures.

First claim

What is claimed is:

1. A device comprising:
a first semiconductor die embedded in a molding compound layer, wherein the first semiconductor die comprises a substrate portion and an interconnect portion over the substrate portion;
a surface-mount device embedded in the molding compound layer, wherein the surface-mount device has a first contact formed along a first sidewall of the surface-mount device and a second contact formed along a second sidewall of the surface-mount device, and wherein a height of the surface-mount device is substantially equal to a height of the substrate portion of the first semiconductor die, and wherein a surface of the surface-mount device, a surface of the molding compound layer and a surface of the substrate portion of the first semiconductor die are substantially level to each other;
a plurality of interconnect structures formed on the molding compound layer, wherein:
the first semiconductor die is electrically coupled to the interconnect structures; and
the surface-mount device is electrically coupled to the interconnect structures through at least one V-shaped via, wherein the at least one V-shaped via is formed of a single conductive material extending from the surface-mount device to a surface of the molding compound layer; and

a plurality of bumps formed on and electrically coupled to the interconnect structures.

2. The device of claim 1 , wherein:
the V-shaped via is of a height less than about 100 um.

3. The device of claim 1 , further comprising:
two sidewalls of the V-shaped form an angle greater than about 55 degrees.

4. The device of claim 1 , wherein:
the surface-mount device comprises two contacts, and wherein the contacts are electrically coupled to the bumps through a conductive channel formed by the V-shaped via and the interconnect structures.

5. The device of claim 1 , wherein:
the interconnect structure comprises a plurality of redistribution lines.

6. The device of claim 1 , wherein:
the surface-mount device is selected from the group consisting of capacitors, resistors, inductors.

7. The device of claim 1 , wherein:
the bumps are formed of solder, copper and any combination thereof.

8. A device comprising:
a surface-mount device embedded in a molding compound layer, wherein:
a top surface of a first side of the surface-mount device is exposed outside the molding compound layer; and
a first metal via and a second metal via are on a second side of the surface-mount device, and wherein the first metal via and the second metal via have non-vertical sidewalls, and wherein the second side of the surface-mount device comprises a first conductive edge region and a second conductive edge region, wherein the first metal via and the second metal via are formed of a same conductive material extending from the surface-mount device to a surface of the molding compound layer;

a first semiconductor die embedded in the molding compound layer, wherein the first semiconductor die comprises a substrate portion and an interconnect portion over the substrate portion, and wherein a height of the first metal via is substantially equal to a height of the substrate portion of the first semiconductor die, and wherein the top surface of the first side of the surface-mount device, a surface of the substrate portion and a surface of the molding compound layer are substantially level to each other;
a plurality of interconnect structures over the molding compound layer; and
a plurality of bumps over the interconnect structures.

9. The device of claim 8 , further comprising:
a first contact and a second contact on the second side of the surface-mount device.

10. The device of claim 9 , wherein:
the first metal via is on and in direct contact with the first contact; and
the second metal via is on and in direct contact with the second contact.

11. The device of claim 8 , wherein:
the first metal via and the second metal via have a trapezoidal shape.

12. The device of claim 8 , wherein:
the first metal via is formed in a first V-shaped cut; and
the second metal via is formed in a second V-shaped cut.

13. The device of claim 8 , further comprising:
a second semiconductor die embedded in the molding compound layer, wherein the second semiconductor die is of a same height as the first semiconductor die.

14. The device of claim 8 , wherein:
the first semiconductor die is higher than the surface-mount device.

15. A device comprising:
a surface-mount device embedded in a molding compound layer, wherein:
the surface-mount device comprises at least one contact on a sidewall of the surface-mount device;
a top surface of a first side of the surface-mount device is exposed outside the molding compound layer; and
a first metal via and a second metal via are on a second side of the surface-mount device, and wherein the first metal via and the second metal via have non-vertical sidewalls;

a first semiconductor die embedded in the molding compound layer, wherein the first semiconductor die comprises a first substrate portion and a first interconnect portion over the first substrate portion, and wherein a height of the surface-mount device is substantially equal to a height of the first substrate portion;
a second semiconductor die embedded in the molding compound layer, wherein the second semiconductor die comprises a second substrate portion and a second interconnect portion over the second substrate portion, and wherein a height of the second substrate portion is substantially equal to the height of the first substrate portion, and wherein the top surface of the first side of the surface-mount device, a surface of the first substrate portion of the first semiconductor die, a surface of the second substrate portion of the second semiconductor die and a surface of the molding compound layer are substantially level to each other; and
a plurality of interconnect structures over the molding compound layer, wherein the first metal via and the second metal via are formed of a same conductive material extending from the surface-mount device to the plurality of interconnect structures, and wherein a first metal line of the plurality of interconnect structures is in contact with the first metal via and the first interconnect portion of the first semiconductor die.

16. The device of claim 15 , wherein:
the non-vertical sidewalls form an angle in a range from about 55 degrees to about 65 degrees.

17. The device of claim 15 , wherein:
a top surface of the first semiconductor die is level with a top surface of the second semiconductor die.

18. The device of claim 15 , wherein:
the interconnect structures comprise a redistribution layer electrically connected to the surface-mount device through the first metal via and the second metal via.

19. The device of claim 15 , wherein:
a top surface of the first semiconductor die is exposed outside the molding compound layer; and
a top surface of the second semiconductor die is exposed outside the molding compound layer.

20. The device of claim 15 , wherein:
the surface-mount device has two contacts coupled to the interconnect structures through the first metal via and the second metal via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hung Jui-Pin
• Yu Chen-Hua
• Lin Jing-Cheng
• Yeh Der-Chyang

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/127

  characterised by arrangements for sealing or adhesion · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title