Conductive structure in semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-9748175-B1
Application number	US-201615355349-A
Country	US
Kind code	B1
Filing date	Nov 18, 2016
Priority date	Nov 18, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming an organosilicon layer over a substrate and etching the organosilicon layer to have a trench. The method for manufacturing a semiconductor structure further includes forming a conductive structure in the trench. In addition, the organosilicon layer is made of a material including Si—C bonding and Si—O bonding, and a ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is greater than about 0.2.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
forming an organosilicon layer over a substrate;
etching the organosilicon layer to form a trench; and
forming a conductive structure in the trench,
wherein the organosilicon layer is made of a material comprising Si—C bonding and Si—O bonding, and a ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is greater than about 0.2.

2. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the ratio of the amount of the Si—C bonding to the amount of the Si—O bonding is in a range of about 0.2 to about 0.25.

3. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein forming an organosilicon layer further comprises:
forming a precursor material over the substrate; and
curing the precursor material to form the organosilicon layer having pores.

4. The method for manufacturing a semiconductor structure as claimed in claim 3 , wherein the precursor material comprises an organosilicon material and a C 3 to C 5 cyclic compound, and the C 3 to C 5 cyclic compound is removed when the precursor material is cured.

5. The method for manufacturing a semiconductor structure as claimed in claim 4 , wherein the C 3 to C 5 cyclic compound comprises substituted or non-substituted C 3 to C 5 cycloalkane, substituted or non-substituted C 3 to C 5 cycloalkene, or combinations thereof.

6. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein the conductive structure has a first width at its top surface and has a second width at its bottom surface, and a ratio of the first width to the second width is smaller than 1.4.

7. The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein a device region is formed in the substrate, and the conductive structure is electrically connected to a transistor formed in the device region.

8. A method for manufacturing an interconnect structure, comprising:
depositing a precursor material over a substrate;
curing the precursor material to form an organosilicon layer;
etching the organosilicon layer to form a trench; and
forming a conductive structure in the trench,
wherein the precursor material comprises an organosilicon material and a C 3 to C 5 cyclic compound, and the C 3 to C 5 cyclic compound is removed when the precursor material is cured.

9. The method for manufacturing a semiconductor structure as claimed in claim 8 , wherein the organosilicon material is Si x C y O z , and a ratio of y to z is in a range from about 0.25 to about 1.

10. The method for manufacturing a semiconductor structure as claimed in claim 8 , wherein the organosilicon material comprises Si—C bonding and Si—O bonding, and a ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is greater than about 0.2.

11. The method for manufacturing a semiconductor structure as claimed in claim 8 , wherein a number of pores are formed in the organosilicon layer.

12. The method for manufacturing a semiconductor structure as claimed in claim 8 , wherein the C 3 to C 5 cyclic compound comprises substituted or non-substituted C 3 to C 5 cycloalkane, substituted or non-substituted C 3 to C 5 cycloalkene, or combinations thereof.

13. The method for manufacturing a semiconductor structure as claimed in claim 10 , wherein the ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is in a range of about 0.2 to about 0.25.

14. The method for manufacturing a semiconductor structure as claimed in claim 8 , wherein some carbons at sidewalls of the trench are removed when the organosilicon layer is etched to form the trench.

15. The method for manufacturing a semiconductor structure as claimed in claim 8 , wherein the conductive structure has a first width at its top surface and has a second width at its bottom surface, and a ratio of the first width to the second width is smaller than 1.4.

16. A semiconductor structure, comprising:
a substrate;
a device region formed in the substrate;
an organosilicon layer formed over the device region; and
a conductive structure formed in the organosilicon layer,
wherein the organosilicon layer is made of a material comprising Si—C bonding and Si—O bonding, and a ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is greater than about 0.2.

17. The semiconductor structure as claimed in claim 16 , wherein the organosilicon layer has a number of pores, and a size of one pore is substantially equal to a size of a C 3 to C 5 cyclic compound.

18. The semiconductor structure as claimed in claim 17 , wherein the C 3 to C 5 cyclic compound comprises substituted or non-substituted C 3 to C 5 cycloalkane, substituted or non-substituted C 3 to C 5 cycloalkene, or combinations thereof.

19. The semiconductor structure as claimed in claim 16 , wherein the ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is in a range of about 0.2 to about 0.25.

20. The semiconductor structure as claimed in claim 16 , wherein the conductive structure has a first width at its top surface and has a second width at its bottom surface, and a ratio of the first width to the second width is smaller than 1.4.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Yi-Jung
• Wu huan-wei
• Tang Chester
• Liou Joung-Wei

Classifications

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10P14/665

  Porous materials · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title