Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof
US-9218964-B2 · Dec 22, 2015 · US
US9748094B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9748094-B2 |
| Application number | US-201113095122-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 27, 2011 |
| Priority date | Sep 3, 2010 |
| Publication date | Aug 29, 2017 |
| Grant date | Aug 29, 2017 |
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A semiconductor compound structure and a method of fabricating the semiconductor compound structure using graphene or carbon nanotubes, and a semiconductor device including the semiconductor compound structure. The semiconductor compound structure includes a substrate; a buffer layer disposed on the substrate, and formed of a material including carbons having hexagonal crystal structures; and a semiconductor compound layer grown and formed on the buffer layer.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a substrate having a first surface; a lower electrode disposed above the first surface of the substrate; a buffer layer disposed on the lower electrode and above the first surface of the substrate, and comprising carbons having hexagonal crystal structures; a light emission layer formed on the buffer layer, and formed of a semiconductor compound; an insulating layer formed to bury a lower portion of the light emission layer on the buffer layer; and an upper electrode formed to cover the light emission layer and the insulating layer. 2. The semiconductor device of claim 1 , further comprising a wetting layer formed on the buffer layer for depositing the light emission layer. 3. The semiconductor device of claim 1 , wherein the light emission layer comprises a first semiconductor layer formed on the buffer layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer. 4. The semiconductor device of claim 1 , wherein the light emission layer comprises a group III-V compound semiconductor material. 5. The semiconductor device of claim 1 , wherein the buffer layer comprises graphene or graphite. 6. The semiconductor device of claim 5 , wherein the light emission layer is formed as a plurality of rods. 7. The semiconductor device of claim 1 , wherein the buffer layer comprises carbon nanotubes (CNTs). 8. The semiconductor device of claim 7 , wherein the light emission layer is formed to cover the CNTs. 9. The semiconductor device of claim 1 , further comprising a resistive layer between the lower electrode and the buffer layer. 10. The semiconductor device of claim 1 , further comprising a catalyst layer on the lower electrode for forming the buffer layer. 11. The semiconductor device of claim 1 , wherein the lower electrode is formed on an upper surface of the substrate. 12. The semiconductor device of claim 1 , wherein the lower electrode is disposed to be separated from the substrate, and the insulating layer fills a space between the substrate and the lower electrode.
Carbon, e.g. diamond-like carbon · CPC title
being non-crystalline insulating materials, e.g. glass or polymers · CPC title
being group IIIA-VIA materials · CPC title
Electricity · mapped topic
Electricity · mapped topic
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