Division operations in memory

Patent metadata

Field	Value
Publication number	US-9747961-B2
Application number	US-201514836673-A
Country	US
Kind code	B2
Filing date	Aug 26, 2015
Priority date	Sep 3, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

First claim

What is claimed is:

1. An apparatus comprising:
a first group of memory cells coupled to a first access line and configured to store a dividend element;
a second group of memory cells coupled to a second access line and configured to store a divisor element; and
a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line;
wherein performing the number of operations comprises:
storing, as a first mask bit-vector, a bit pattern indicating at least one of a most significant bit (MSB) and a least significant bit (LSB) of at least one of a dividend bit-vector comprising the dividend element and a divisor bit-vector comprising the divisor element;
storing, as a second mask bit-vector, a bit pattern indicating at least one of the most significant bit (MSB) and the least significant bit (LSB) of multiple elements of at least one of the dividend bit-vector and the divisor bit-vector; and
performing a logical operation on the first mask bit-vector and a bit-vector stored in the sensing circuitry.

2. The apparatus of claim 1 , wherein the number of operations comprises a number of AND operations, OR operations, and SHIFT operations.

3. The apparatus of claim 2 , wherein the sensing circuitry comprises a number of transistors formed on pitch with the memory cells.

4. The apparatus of claim 3 , wherein the sensing circuitry comprises a sense amplifier and a compute component.

5. The apparatus of claim 4 , wherein the sense amplifier comprises a primary latch and the compute component comprises a secondary latch.

6. A method for performing division operations, comprising:
performing, in parallel and without transferring data via an input/output (I/O) line, a plurality of division operations on:
a plurality of dividend elements stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array; and
a plurality of divisor elements stored in a second group of memory cells coupled to a second access line and to the number of sense lines of the memory array; and

providing a plurality of quotient elements and a plurality of remainder elements;
wherein performing the plurality of division operations comprises:
storing, as a first mask bit-vector, a bit pattern indicating at least one of a most significant bit (MSB) and a least significant bit (LSB) of at least one of a dividend bit-vector comprising the plurality of dividend elements and a divisor bit-vector comprising the plurality of divisor elements;
storing, as a second mask bit-vector, a bit pattern indicating at least one of the most significant bit (MSB) and the least significant bit (LSB) of respective elements of at least one of the dividend bit-vector and the divisor bit-vector; and
performing a logical operation on the first mask bit-vector and a bit-vector stored in sensing circuitry coupled to the memory array.

7. The method of claim 6 , wherein the plurality of dividend elements are a plurality of first values and the plurality of divisor elements are a plurality of second values.

8. The method of claim 6 , wherein a number of operations used to perform the plurality of division operations in parallel is the same as a number of operations used to perform any one of the plurality of division operations.

9. An apparatus comprising:
a memory array comprising:
a first group of memory cells coupled to a first access line and configured to store a plurality of dividend elements as a dividend bit-vector; and
a second group of memory cells coupled to a second access line and configured to store a plurality of divisor elements as a divisor bit-vector; and

a controller configured to control sensing circuitry to:
perform a plurality of division operations by dividing, in parallel, each one of the plurality of dividend elements by a respective one of the plurality of divisor elements;
store a plurality of results of the plurality of division operations in a third group of memory cells without transferring data via an input/output (I/O) line; and
wherein performing the plurality of division operations comprises:
storing, as a first mask bit-vector, a bit pattern indicating at least one of a most significant bit (MSB) and a least significant bit (LSB) of at least one of the dividend bit-vector and the divisor bit-vector;
storing, as a second mask bit-vector, a bit pattern indicating at least one of the most significant bit (MSB) and the least significant bit (LSB) of respective elements of at least one of the dividend bit-vector and the divisor bit-vector; and

performing a logical operation on the first mask bit-vector and a bit-vector stored in sensing circuitry coupled to the memory array.

10. The apparatus of claim 9 , wherein the plurality of results comprise a plurality of bit-vectors that represent at least one of a plurality of quotient elements and a plurality of remainder elements.

11. The apparatus of claim 9 , wherein the third group of memory cells is a same group of memory cells as at least one of:
the first group of memory cells coupled to the first access line; and
the second group of memory cells coupled to the second access line.

12. The apparatus of claim 9 , wherein each of the plurality of division operations is performed on a different element pair including corresponding elements from the plurality of dividend elements and the plurality of divisor elements.

13. A method for dividing elements comprising:
performing a plurality of division operations in parallel on:
a plurality (M) of dividend elements stored in a first group of memory cells coupled to a first access line and to a number (X) of sense lines; and
a plurality (M) of divisor elements stored in a second group of memory cells coupled to a second access line and to the X sense lines;
wherein the plurality of division operations are performed by performing a number of AND operations, OR operations, and SHIFT operations without transferring data via an input/output (I/O) line; and

storing, in parallel and without transferring data via the I/O line, a plurality of results of the division operations in:
a third group of memory cells coupled to a third access line and to the X sense lines; and
a fourth group of memory cells coupled to a fourth access line and to the X sense lines;

wherein the plurality of results include a plurality (M) of quotient elements stored in the third group of memory cells and a plurality (M) of remainder elements stored in the fourth group of memory cells;
wherein the method includes creating a static mask bit-vector and a dynamic mask bit-vector that identify a most significant bit (MSB) for each of the M dividend elements and the M divisor elements;
wherein the M dividend elements are stored as a dividend bit-vector, the M divisor elements are stored as a divisor bit-vector, the M quotient elements are stored as a quotient bit-vector, and the M remainder elements are stored as a remainder bit-vector;
wherein performing the plurality of division operations includes performing a number (E) of iterations of operations; and
wherein performing each of the E iterations of operations comprises:
storing the dynamic mask bit-vector in the sensing circuitry and in a group of memory cells that store a current dividend bit-vector;
performing a number (P) of iterations of operations comprising:
shifting the current bit-vector stored in the sensing circuitry;
inverting the shifted bit-vector in the sensing circuitry;
performing a first logical operation on the inverted bit

Assignees

• Micron Technology Inc

Inventors

• Tiwari Sanjay

Classifications

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F12/02

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title