Reducing power for 3D workloads

Patent metadata

Field	Value
Publication number	US-9747657-B2
Application number	US-201113976906-A
Country	US
Kind code	B2
Filing date	Nov 30, 2011
Priority date	Nov 30, 2011
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Various embodiments are presented herein that may reduce the workload of a system tasked with delivering frames of video data to a display generated by applications executing within the system. Applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). The CPU and/or GPU may be responsible for actually generating the frames at the specified FPS. These frames are then delivered to a display communicatively coupled with the system for rendering. Reducing the frame rate (FPS) may reduce the work being performed by the system because fewer frames may be generated within a given time period. This may be especially advantageous when the system is operating on battery power because it can extend the life of the battery.

First claim

What is claimed is:

1. An apparatus comprising:
a processor circuit; and
a graphics driver operative on the processor circuit to execute an application that generates frames of video content at a defined frame rate associated with a defined frame rate execution time, the graphics driver operative to:
calculate a time elapsed between a previous frame and a current frame to determine a current frame rate execution time;
calculate a time differential by subtracting the current frame rate execution time from the defined frame rate execution time; and
switch a processor thread associated with the application generating the current frame to a sleep state while the time differential is greater than zero (0).

2. The apparatus of claim 1 , the graphics driver operative to:
present the current frame to a display when the time differential reaches zero (0).

3. The apparatus of claim 2 , comprising:
a display communicatively coupled with the processor circuit, the display operative to render the current frame presented by the graphics driver.

4. The apparatus of claim 1 , comprising a battery coupled to the processor circuit, the battery operative to provide power to the processor circuit.

5. The apparatus of claim 1 , the defined frame rate being a minimum frame rate supportable by the application.

6. A apparatus comprising:
a processor circuit; and
a graphics driver operative on the processor circuit to execute an application that generates frames of video content at a defined frame rate associated with a defined frame rate execution time, the graphics driver operative to:
calculate a time elapsed between a previous frame and a current frame to determine a current frame rate execution time;
fix a reduced frame rate execution time that is between the defined frame rate execution time and the current frame rate execution time;
calculate a time differential by subtracting the current frame rate execution time from the reduced frame rate execution time; and
switch a processor thread associated with the application generating the current frame to a sleep state while the time differential is greater than zero (0).

7. The apparatus of claim 6 , comprising the graphics driver operative to:
present the current frame to a display when the time differential reaches zero (0).

8. The apparatus of claim 7 , comprising:
a display communicatively coupled with the graphics driver, the display operative to render the current frame presented by the graphics driver.

9. The apparatus of claim 6 , comprising a battery operative to power the processor circuit.

10. The apparatus of claim 6 , the graphics driver operative to determine a percentage level of remaining battery power.

11. The apparatus of claim 10 , the graphics driver operative to adjust the reduced frame rate lower when the percentage level of remaining battery power is lower than a threshold percentage level.

12. The apparatus of claim 6 , the defined frame rate being a minimum frame rate supportable by the application.

13. A method, comprising:
executing an application on a central processing unit (CPU), the application operative to generate frames of video content at a defined frame rate associated with a defined frame rate execution time;
calculating a time elapsed between a previous frame and a current frame to determine a current frame rate execution time;
calculating a time differential by subtracting the current frame rate execution time from the defined frame rate execution time; and
switching a CPU thread associated with the application generating the current frame to a sleep state while the time differential is greater than zero (0).

14. The method of claim 13 , comprising:
switching the CPU thread to a sleep state only while the CPU is operating on battery power.

15. The method of claim 13 , comprising:
presenting the current frame to a display when the time differential reaches zero (0).

16. The method of claim 13 , wherein the defined frame rate is a minimum frame rate supportable by the application.

17. A method, comprising:
executing an application on a central processing unit (CPU), the application operative to generate frames of video content at a defined frame rate associated with a defined frame rate execution time;
calculating a time elapsed between a previous frame and a current frame to determine a current frame rate execution time;
fixing a reduced frame rate execution time that is between the defined frame rate execution time and the current frame rate execution time;
calculating a time differential by subtracting the current frame rate execution time from the reduced frame rate execution time; and
switching a CPU thread associated with the application generating the current frame to a sleep state while the time differential is greater than zero (0).

18. The method of claim 17 , comprising:
switching the CPU thread to a sleep state only while the CPU is operating on battery power.

19. The method of claim 17 , comprising:
presenting the current frame to a display when the time differential reaches zero (0).

20. The method of claim 17 , comprising:
determining a percentage level of remaining battery power while the CPU is operating on battery power.

21. The method of claim 17 , comprising:
adjusting the reduced frame rate lower when the percentage level of remaining battery power is lower than a threshold percentage level.

22. The method of claim 17 , wherein the defined frame rate is a minimum frame rate supportable by the application.

23. An article of manufacture comprising a computer-readable storage medium containing instructions that when executed cause a system to:
execute an application on a processor circuit, the application operative to generate frames of video content at a frame rate associated with a frame rate execution time;
determine a current frame rate execution time;
determine a time differential between the current frame rate execution time and the defined frame rate execution time; and
switch a CPU thread associated with the application generating the current frame to a sleep state for a period equal to the time differential.

24. The article of claim 23 containing instructions that when executed cause a system to:
switch the CPU thread to a sleep state only while the processor circuit is operating on battery power.

25. The article of claim 23 containing instructions that when executed cause a system to:
present the current frame to a display when the time differential reaches zero (0).

26. The article of claim 23 , wherein the defined frame rate is a minimum frame rate supportable by the application.

27. An article of manufacture comprising a computer-readable storage medium containing instructions that when executed cause a system to:
execute an application on a central processing unit (CPU), the application operative to generate frames of video content at a defined frame rate associated with a defined frame rate execution time;
determine a current frame rate execution time;
fix a reduced frame rate execution time that is lower than the current frame rate execution time;
determine a time differential between the current frame rate execution time and the reduced frame rate execution time; and
switch a CPU thread associated with the application generating the current frame to a sleep state for a period equal to the time differential

Assignees

• Apodaca Michael
• Intel Corp

Inventors

• Apodaca Michael

Classifications

• G06F1/3212 Primary

  Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title

• Y02B60/1242

  Cross-Sectional Technologies · mapped topic

• G06F1/329

  by task scheduling · CPC title

• Y02B60/144

  Cross-Sectional Technologies · mapped topic

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title