Optimizing placement of circuit resources using a globally accessible placement memory

Patent metadata

Field	Value
Publication number	US-9747400-B2
Application number	US-201615371251-A
Country	US
Kind code	B2
Filing date	Dec 7, 2016
Priority date	Mar 24, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.

First claim

What is claimed is:

1. A computer system comprising:
one or more processors;
one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising instructions to execute a method comprising:
partitioning a logic network comprising a plurality of logic elements into a plurality of logic partitions;
launching a plurality of placement optimization threads that correspond to the plurality of logic partitions;
allocating memory that is accessible to the plurality of placement optimization threads to provide a globally accessible placement memory;
reserving a placement location for at least a portion of the plurality of logic elements via the globally accessible placement memory; and
wherein each placement optimization thread of the plurality of placement optimization threads is configured to conduct the operations of:
determining a desired location for a logic element of the plurality of logic elements, wherein the logic element is within a logic partition that corresponds to the placement optimization thread,
reserving, via the globally accessible placement memory, a plurality of potential locations for the logic element that are proximate to the desired location,
determining a best location from the plurality of potential locations,
releasing each of the plurality of potential locations that are not the best location,
placing the logic element at the best location, and
wherein reserving a potential location comprises locking at least a portion of the globally accessible placement memory, inserting a thread identifier within at least one entry of an owning thread array stored within the globally accessible placement memory, and inserting at least one bit within a reserved locations bitmap stored within the globally accessible placement memory, and unlocking the portion of the globally accessible placement memory that was locked to reserve the potential location.

Assignees

• IBM

Inventors

• Hathaway David J
• Hieter Nathaniel D
• Ramji Shyam
• Suess Alexander J

Classifications

• G06F2111/02

  CAD in a network environment, e.g. collaborative CAD or distributed simulation · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F17/505 Primary

  Physics · mapped topic

• G06F17/5072

  Physics · mapped topic

• G06F17/5022

  Physics · mapped topic