Memory rank and ODT configuration in a memory system

Patent metadata

Field	Value
Publication number	US-9747230-B2
Application number	US-201314408955-A
Country	US
Kind code	B2
Filing date	Oct 14, 2013
Priority date	Oct 15, 2012
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.

First claim

What is claimed is:

1. A memory module, comprising:
a data line;
a connector pin coupled to the data line;
a first memory package coupled to the data line, the first memory package corresponding to a first number of memory ranks; and
a second memory package coupled to the data line, the second memory package corresponding to a second number of memory ranks that is different than the first number of memory ranks,
wherein a length of the data line from the connector pin to the first memory package is substantially greater than a length of the data line from the connector pin to the second memory package.

2. The memory module of claim 1 , wherein the length of the data line from the connector pin to the first memory package is greater than the length of the data line from the connector pin to the second memory package by at least ten percent of a height of the second memory package.

3. The memory module of claim 1 , wherein the first memory package and the second memory package are on a same side of the memory module.

4. The memory module of claim 1 , wherein the first memory package and the second memory package are on opposing sides of the memory module.

5. The memory module of claim 1 , wherein the first number of memory ranks is one memory rank and the second number of memory ranks is two memory ranks.

6. The memory module of claim 1 , wherein on-die termination (ODT) of the first memory package is disabled and ODT of the second memory package is enabled for write operations to the first memory package.

7. A memory system, comprising:
a first memory module that includes a first memory package corresponding to a first number of memory ranks and a second memory package corresponding to a second number of memory ranks that is different than the first number of memory ranks; and
a memory controller coupled to the first memory package and second memory package via a common data line,
wherein a length of the data line from the memory controller to the first memory package is substantially greater than a length of the data line from the memory controller to the second memory package.

8. The memory system of claim 7 , wherein the first number of memory ranks is a single memory rank and the second number of memory ranks is two memory ranks.

9. The memory system of claim 7 , wherein the memory controller disables on-die termination (ODT) of the first memory package and enables ODT of the second memory package for write operations to the first memory package.

10. The memory system of claim 7 , wherein the memory controller enables on-die termination (ODT) of the first memory package and disables the ODT of the second memory package for write operations to the second memory package.

11. The memory system of claim 7 , wherein the memory controller enables the on-die termination (ODT) of the first memory package and disables the ODT of the second memory package for read operations from the second memory package.

12. The memory system of claim 7 , further comprising:
a second memory module that includes a third memory package corresponding to the first number of memory ranks and a fourth memory package corresponding to the second number of memory ranks,
wherein the memory controller transfers data with the third memory package and the fourth memory package via the common data line.

13. The memory system of claim 12 , wherein a third length of the data line between the memory controller and the third memory package is substantially greater than a fourth length of the data line between the memory controller and the fourth memory package.

14. The memory system of claim 12 , wherein the second memory module is positioned further from the memory controller than the first memory module.

15. The memory system of claim 12 , wherein the memory controller enables the on-die termination (ODT) of the first memory package and disables the ODT of the second memory package for both read and write operations to the third memory package and the fourth memory package of the second memory module.

16. The memory module of claim 1 , wherein the second number of memory ranks is greater than the first number of memory ranks.

17. The memory system of claim 7 , wherein the second number of memory ranks is greater than the first number of memory ranks.

Assignees

• Rambus Inc

Inventors

• Han Minghui
• Amirkhany Amir
• Kollipara Ravindranath
• Schmitt Ralf Michael

Classifications

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F3/0635

  by changing the path, e.g. traffic rerouting, path reconfiguration · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title