Method and system for memory access protection

Patent metadata

Field	Value
Publication number	US-9747146-B2
Application number	US-201414248638-A
Country	US
Kind code	B2
Filing date	Apr 9, 2014
Priority date	May 16, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Aspects of the disclosure provide a method for null address handling. The method includes compiling code without adding a null check code before a memory access code, storing a first address of the memory access code in association with a second address of a handling code for null address, determining, in response to an exception that occurs at the first address during an execution of the compiled code, the second address based on the stored information, and executing the handling code at the second address.

First claim

What is claimed is:

1. A method for null address handling, comprising:
compiling code to generate native code without adding a null check code before a memory access code in the native code and generate an entry in a table including a first address of the memory access code and a second address of a null handling code associated with the memory access at the first address:
determining, in response to an exception that occurs at the first address during an execution of the compiled code, the second address based on the stored information, and
executing the handling code at the second address.

2. The method of claim 1 , wherein determining, in response to the exception that occurs at the first address during the execution of the compiled code, the second address based on the stored information further comprises:
searching for the first address in the table; and
outputting the second address stored in association with the first address.

3. The method of claim 1 , wherein determining, in response to the exception that occurs at the first address during the execution of the compiled code, the second address based on the stored information further comprises:
determining the second address in association with the first address by a kernel.

4. The method of claim 1 , wherein compiling the code without adding the null check code before the memory access code further comprises at least one of:
compiling the code without adding the null check code before an array member access code; and
compiling the code without adding the null check code before an object access code.

5. The method of claim 1 , wherein compiling the code without adding the null check code before the memory access code further comprises:
compiling, by a Java virtual machine, the code without adding the null check code before the memory access code.

6. The method of claim 5 , wherein storing the first address of the memory access code in association with the second address of the handling code for the null address further comprises:
storing, by the Java virtual machine, the first address of the memory access code in association with the second address of the handling code for the null address.

7. The method of claim 6 , wherein determining, in response to the exception that occurs at the first address during the execution of the compiled code, the second address based on the stored information further comprises:
determining, by a kernel, the second address in association with the first address.

8. The method of claim 7 , wherein executing the handling code at the second address further comprises:
returning to the Java virtual machine to execute the handling code at the second address.

9. A non-transitory computer readable medium storing program instructions for causing a processor to execute operations for null address handling, the operations comprising:
compiling code to generate native code without adding a null check code before a memory access code in the native code and generate an entry in a table including a first address of the memory access code and a second address of a null handling code associated with the memory access at the first address;
determining, in response to an exception that occurs at the first address during an execution of the compiled code, the second address based on the stored information, and
executing the handling code at the second address.

10. The non-transitory computer readable medium of claim 9 , wherein the operation of determining, in response to the exception that occurs at the first address during the execution of the compiled code, the second address based on the stored information further comprises:
searching for the first address in the table; and
outputting the second address stored in association with the first address.

11. The non-transitory computer readable medium of claim 9 , wherein the operation of determining, in response to the exception that occurs at the first address during the execution of the compiled code, the second address based on the stored information further comprises:
determining the second address in association with the first address by a kernel.

12. The non-transitory computer readable medium of claim 9 , wherein the operation of compiling the code without adding the null check code before the memory access code further comprises at least one of:
compiling the code without adding the null check code before an array member access code; and
compiling the code without adding the null check code before an object access code.

13. The non-transitory computer readable medium of claim 9 , wherein the operation of compiling the code without adding the null check code before the memory access code further comprises:
compiling, by a Java virtual machine, the code without adding the null check code before the memory access code.

14. The non-transitory computer readable medium of claim 13 , wherein the operation of storing the first address of the memory access code in association with the second address of the handling code for the null address further comprises:
storing, by the Java virtual machine, the first address of the memory access code in association with the second address of the handling code for the null address.

15. The non-transitory computer readable medium of claim 14 , wherein the operation of determining, in response to the exception that occurs at the first address during the execution of the compiled code, the second address based on the stored information further comprises:
determining, by a kernel, the second address in association with the first address.

16. The non-transitory computer readable medium of claim 15 , wherein the operation of executing the handling code at the second address further comprises:
returning to the Java virtual machine to execute the handling code at the second address.

17. A method for null address handling, comprising:
compiling, by a Java virtual machine, a code to generate native code without adding a null check code before a memory access code in the native code and generate an entry in a table including a first address of the memory access code and a second address of a null handling code associated with the memory access at the first address;
exiting the Java virtual machine in response to an exception that occurs at the first address during the execution of the compiled code to let a kernel to determine the second address based on the stored information; and
returning to the Java virtual machine with the determined second address to execute the handling code at the second address.

Assignees

• Marvell World Trade Ltd

Inventors

• Huang Haitao
• Fan Ye

Classifications

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F9/4552

  Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title