Method and apparatus for performing a shift and exclusive or operation in a single instruction

Patent metadata

Field	Value
Publication number	US-9747105-B2
Application number	US-65370409-A
Country	US
Kind code	B2
Filing date	Dec 17, 2009
Priority date	Dec 17, 2009
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

First claim

What is claimed is:

1. A processor comprising:
a decoder to decode a shift and exclusive OR (XOR) instruction having a first source operand to specify or to store a first value, a second source operand to specify or to store a shift amount and a third source operand to specify or to store a second value; and
an execution unit to perform the shift and XOR instruction,
wherein responsive to the shift and XOR instruction the first value is to be shifted by the shift amount and the shifted first value is to be XOR'ed with the second value to produce a result of the shift and XOR instruction,
wherein the second value is to be specified or stored separately from all data to be shifted by the shift amount, and
wherein the first source operand is to specify or to store said all data to be shifted in response to the instruction.

2. The processor of claim 1 , wherein the first value is to be shifted left.

3. The processor of claim 1 , wherein the first value is to be shifted right.

4. The processor of claim 1 , wherein the first value is to be shifted logically.

5. The processor of claim 1 , wherein the first value is to be shifted arithmetically.

6. The processor of claim 1 , wherein the execution unit comprises a shifter and an XOR circuit.

7. The processor of claim 1 , wherein the shift and XOR instruction includes a first field to store the second value.

8. The processor of claim 1 , wherein the first value is included in a packed data operand.

9. A system comprising:
a dynamic random access memory (DRAM) to store a first instruction to perform a shift and exclusive OR (XOR) operation; and
a processor to execute the first instruction to perform the shift and XOR operation, the first instruction having a first source operand to specify or to store a first value, a second source operand to specify or to store a shift amount and a third source operand to specify or to store a second value,
wherein responsive to the first instruction the first value is to be shifted by the shift amount and the shifted first value is to be XOR'ed with the second value to produce a result of the first instruction,
wherein the second value does not include data to be shifted by the shift amount, and
wherein the first source operand is to provide all data to be shifted in response to the instruction.

10. The system of claim 9 , wherein the first value is to be shifted left.

11. The system of claim 9 , wherein the first value is to be shifted right.

12. The system of claim 9 , wherein the first value is to be shifted logically.

13. The system of claim 9 , wherein the first value is to be shifted arithmetically.

14. The system of claim 9 , wherein the processor comprises a shifter and an XOR circuit.

15. The system of claim 9 , wherein the shift and XOR instruction includes a first field to store the second value.

16. The system of claim 9 , wherein the first value is included in a packed data operand.

17. A method comprising:
decoding a shift and exclusive OR (XOR) instruction having a first source operand that specifies or stores a first value, a second source operand that specifies or stores a shift amount and a third source operand that specifies or stores a second value; and
responsive to the shift and XOR instruction, shifting the first value by the shift amount and XOR'ing the shifted first value with the second value to produce a result of the shift and XOR instruction, and
wherein the second value is stored in a location not used to store data that is shifted by the shift amount, and
wherein data from the third source operand is not shifted in response to the shift and XOR instruction.

18. The method of claim 17 , wherein the first value is shifted left.

19. The method of claim 17 , wherein the first value is shifted right.

20. The method of claim 17 , wherein the first value is shifted logically.

21. The method of claim 17 , wherein the first value is shifted arithmetically.

22. The method of claim 17 , wherein decoding includes decoding the shift and XOR instruction that includes a first field to store the second value.

23. The method of claim 17 , wherein the first value has a packed datatype.

24. A non-transitory machine-readable medium having stored thereon instructions including an instruction having a first source operand to specify or to store a first value, a second source operand to specify or to store a shift amount and a third source operand to specify or to store a second value, the instruction if performed by a machine is to cause the machine to perform a method comprising:
shifting the first value by the shift amount; and
XORing the shifted first value with the second value to generate a result of the instruction,
wherein the second value is to be specified or stored separately from data to be shifted by the shift amount, and
wherein data from the third source operand is not to be shifted in response to the instruction.

25. The machine-readable medium of claim 24 , wherein the first value is to be shifted left.

26. The machine-readable medium of claim 24 , wherein the first value is to be shifted right.

27. The machine-readable medium of claim 24 , wherein the first value is to be shifted logically.

28. The machine-readable medium of claim 24 , wherein the first value is to be shifted arithmetically.

29. The machine-readable medium of claim 24 , wherein the shift and XOR instruction includes a first field to store the second value.

30. The machine-readable medium of claim 24 , wherein the first value has a packed datatype.

31. The processor of claim 1 , wherein the processor comprises a general-purpose processor, further comprising a reorder buffer, and wherein the first value is to be left shifted by the shift amount.

32. The system of claim 9 , wherein the DRAM stores a second instruction to check for a minimum number of leading zeros in the result.

33. A processor comprising:
a decoder to decode a shift and exclusive OR (XOR) instruction having a first source operand to specify or to store a first value, a second source operand to specify or to store a shift amount and a third source operand to specify or to store a second value; and
an execution unit to perform the shift and XOR instruction,
wherein responsive to the shift and XOR instruction the first value is to be shifted by the shift amount and the shifted first value is to be XOR'ed with the second value to produce a result of the shift and XOR instruction,
wherein the second value is to be specified or stored separately from data to be shifted by the shift amount, and
wherein data from the third source operand is not to be shifted in response to the shift and XOR instruction.

34. The processor of claim 33 , wherein the first value is to be shifted left.

35. The processor of claim 33 , wherein the first value is to be shifted arithmetically.

36. The processor of claim 33 , wherein the processor comprises a general-purpose processor, further comprising a reorder buffer, and wherein the first value is to be left shifted by the shift amount.

37. The processor of claim 33 , wherein the first value is included in a packed data operand.

38. A processor comprising:
a decoder to decod

Assignees

• Gopal Vinodh
• Guilford James D
• Ozturk Erdine
• Feghali Wajdi K
• Wolrich Gilbert M
• Dixon Martin G
• Intel Corp

Inventors

• Gopal Vinodh
• Guilford James D
• Ozturk Erdine
• Feghali Wajdi K
• Wolrich Gilbert M
• Dixon Martin G

Classifications

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3816

  Instruction alignment, e.g. cache line crossing · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/3893 Primary

  controlled in tandem, e.g. multiplier-accumulator · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title