Supporting runtime D3 and buffer flush and fill for a peripheral component interconnect device

Patent metadata

Field	Value
Publication number	US-9746910-B2
Application number	US-201615005488-A
Country	US
Kind code	B2
Filing date	Jan 25, 2016
Priority date	Dec 26, 2012
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Particular embodiments described herein provide for an apparatus that includes a means for determining a power state for a device connected to a system, a means for determining that the device should change power states, and means for sending a signal to the device to put the device in a D3-cold state while the system is a GO/SO state. In an embodiment, the device is a peripheral component interconnect (PCI) device. Also, the particular example implementation can include means for sending a PCIRST# signal from the device to a controller to cause the device to exit the D3-cold state, wherein the PCIRST# signal is received at a pin on the controller that is different than a designated PCIRST# signal pin.

First claim

What is claimed is:

1. A method for managing power and performance, comprising:
determining a power state for a device connected to a system;
determining that the device should change power states;
sending a signal to the device to put the device in a D3-cold state while the system is a GO/SO state; and
sending a PCIRST# signal from the device to a controller to cause the device to exit the D3-cold state, wherein the PCIRST# signal is received at a pin on the controller that is different than a designated PCIRST# signal pin.

2. The method of claim 1 , wherein the device is a peripheral component interconnect (PCI) device.

3. The method of claim 1 , further comprising:
sending a WAKE# signal from a controller to the device to cause the device to exit the D3-cold state, wherein the WAKE# signal was sent from a designated WAKE# signal pin on the controller.

4. The method of claim 3 , wherein the WAKE# signal was not sent to other devices in the system.

5. The method of claim 1 , further comprising:
sending a WAKE# signal from the device to a controller to cause the device to exit the D3-cold state, wherein the WAKE# signal is received at a pin on the controller that is different than a designated WAKE# signal pin.

6. The method of claim 1 , wherein the PCIRST# signal was not sent to other devices in the system.

7. An apparatus comprising at least one processor and at least one memory, the at least one memory comprising instructions that, when executed by the processor, cause the apparatus to:
determine a power state for a device connected to a system;
determine that the device should change power states;
send a signal to the device to put the device in a D3-cold state while the system is a GO/SO state; and
send a PCIRST# signal from the device to a controller to cause the device to exit the D3-cold state, wherein the PCIRST# signal is received at a pin on the controller that is different than a designated PCIRST# signal pin.

8. The apparatus of claim 7 , wherein the device is a peripheral component interconnect (PCI) device.

9. The apparatus of claim 7 , further comprising instructions that, when executed by the processor, cause the apparatus to:
send a WAKE# signal from a controller to the device to cause the device to exit the D3-cold state, wherein the WAKE# signal was sent from a designated WAKE# signal pin on the controller.

10. The apparatus of claim 9 , wherein the WAKE# signal was not sent to other devices in the system.

11. The apparatus of claim 7 , further comprising instructions that, when executed by the processor, cause the apparatus to:
sending a WAKE# signal from the device to a controller to cause the device to exit the D3-cold state, wherein the WAKE# signal is received at a pin on the controller that is different than a designated WAKE# signal pin.

12. The apparatus of claim 7 , wherein the PCIRST# signal was not sent to other devices in the system.

13. A non-transitory computer readable medium comprising instructions that, when executed by a processor, cause an apparatus to:
determine a power state for a device connected to a system;
determine that the device should change power states; and
send a signal to the device to put the device in a D3-cold state while the system is a GO/SO state; and
send a PCIRST# signal from the device to a controller to cause the device to exit the D3-cold state, wherein the PCIRST# signal is received at a pin on the controller that is different than a designated PCIRST# signal pin.

14. The computer readable medium of claim 13 , wherein the device is a peripheral component interconnect (PCI) device.

15. The computer readable medium of claim 13 , further comprising instructions that, when executed by the processor, cause the apparatus to:
send a WAKE# signal from a controller to the device to cause the device to exit the D3-cold state, wherein the WAKE# signal was sent from a designated WAKE# signal pin on the controller.

16. The computer readable medium of claim 15 , wherein the WAKE# signal was not sent to other devices in the system.

17. The computer readable medium of claim 13 , further comprising instructions that, when executed by the processor, cause the apparatus to:
send a WAKE# signal from the device to a controller to cause the device to exit the D3-cold state, wherein the WAKE# signal is received at a pin on the controller that is different than a designated WAKE# signal pin.

18. The computer readable medium of claim 13 , wherein the PCIRST# signal was not sent to other devices in the system.

19. An apparatus, comprising:
means for determining a power state for a device connected to a system;
means for determining that the device should change power states;
means for sending a signal to the device to put the device in a D3-cold state while the system is a GO/SO state; and
means for sending a PCIRST# signal from the device to a controller to cause the device to exit the D3-cold state, wherein the PCIRST# signal is received at a pin on the controller that is different than a designated PCIRST# signal pin.

20. The apparatus of claim 19 , wherein the device is a peripheral component interconnect (PCI) device.

Assignees

• Intel Corp

Inventors

• Gough Robert
• Ebrahim Ismail

Classifications

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• Y02B60/1282

  Cross-Sectional Technologies · mapped topic

• G06F1/266

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title