Cmos-based process for manufacturing a semiconductor gas sensor

US9746437B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9746437-B1
Application numberUS-201715398025-A
CountryUS
Kind codeB1
Filing dateJan 4, 2017
Priority dateAug 3, 2016
Publication dateAug 29, 2017
Grant dateAug 29, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A CMOS-based process for manufacturing a semiconductor gas sensor includes the steps of: I) providing a semi-product, II) etching a substrate to remove a portion of the substrate and a portion of a first insulation layer so as to form a gas-sensing cavity, thereby to expose at least one sensing electrode; and III) depositing a gas-sensitive layer to cover the at least one sensing electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A CMOS-based process for making a semi-product for manufacturing a semiconductor gas sensor, comprising the steps of: (a) preparing a substrate made from a semiconductor material and having a first surface and a second surface opposite to the first surface; (b) depositing a first insulation layer on the first surface of the substrate; (c) forming in an integrated circuit area an N-type doped region and a P-type doped region under the first surface of the substrate; (d) simultaneously forming on the first insulation layer a plurality of gate electrodes and at least one sensing electrode using a depositable conductive material, each of the gate electrodes being located above a corresponding one of the N-type and P-type doped regions, the at least one sensing electrode being located in a sensing area; (e) depositing a second insulation layer on the first insulation layer so as to cover the gate electrodes and the at least one sensing electrode; (f) forming a P-type doped source sub-region and a P-type doped drain sub-region in the N-type doped region and an N-type doped source sub-region and an N-type doped drain sub-region in the P-type doped region; (g) forming a plurality of via holes each of which extends through the first and second insulation layers and communicates with a corresponding one of the P-type doped source sub-region, the P-type doped drain sub-region, the N-type doped source sub-region, and the N-type doped drain sub-region; (h) simultaneously forming on the second insulation layer a micro-heater and a plurality of connecting ends of connecting portions using a resistive heating material, the micro-heater being in the sensing area and above the at least one sensing electrode, each of the connecting portions extending to fill a corresponding one of the via holes; and (i) depositing a third insulation layer on the second insulation layer to cover the micro-heater while leaving the connecting ends of the connecting portions exposed. 2. The method according to claim 1 , wherein the depositable conductive material is polycrystalline silicon. 3. The method according to claim 1 , wherein the resistive heating material is selected from the group consisting of tantalum nitride, tungsten, and a combination thereof. 4. A CMOS-based process for manufacturing a semiconductor gas sensor, comprising the steps of: (I) providing a semi-product made by the method according to claim 1 ; (II) etching from the second surface of the substrate to remove a portion of the substrate and a portion of the first insulation layer so as to form a gas-sensing cavity, thereby to expose the at least one sensing electrode; and (III) depositing a gas-sensitive layer to cover the at least one sensing electrode. 5. The method according to claim 4 , wherein in step (II), the first insulation layer is etched via deep reactive ion etching or inductively coupled plasma etching. 6. A semiconductor gas sensor manufactured by the method according to claim 4 .

Assignees

Inventors

Classifications

  • by chemical means · CPC title

  • Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate · CPC title

  • Processes for functionalising a surface, e.g. provide the surface with specific mechanical, chemical or biological properties · CPC title

  • Investigating or analysing materials by the use of electric, electrochemical, or magnetic means (G01N3/00 – G01N25/00 take precedence; measurement or testing of electric or magnetic variables or of electric or magnetic properties of materials G01R) · CPC title

  • G01N27/128Primary

    Microapparatus · CPC title

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What does patent US9746437B1 cover?
A CMOS-based process for manufacturing a semiconductor gas sensor includes the steps of: I) providing a semi-product, II) etching a substrate to remove a portion of the substrate and a portion of a first insulation layer so as to form a gas-sensing cavity, thereby to expose at least one sensing electrode; and III) depositing a gas-sensitive layer to cover the at least one sensing electrode.
Who is the assignee on this patent?
Univ Nat Chiao Tung
What technology area does this patent fall under?
Primary CPC classification B81C1/00206. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Aug 29 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).