Method of fabricating wafer

US9745667B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9745667-B2
Application numberUS-201214128855-A
CountryUS
Kind codeB2
Filing dateJun 22, 2012
Priority dateJun 22, 2011
Publication dateAug 29, 2017
Grant dateAug 29, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method of fabricating a wafer according to the embodiment comprises the steps of growing an wafer on a surface of the wafer in a growth temperature; and cooling the wafer after the wafer has been grown, wherein a stepwise cooling is performed when cooling the wafer.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of fabricating a wafer, the method comprising: growing a single crystal layer on a surface of the wafer at a growth temperature; cooling the wafer after the single crystal layer has been grown; and annealing the wafer, wherein the annealing of the wafer is performed at a temperature corresponding to or lower than the growth temperature, wherein the growing of the single crystal layer and the annealing of the wafer are performed in the same chamber in situ, and wherein the wafer is cut at an angle of 4° or 8°. 2. The method of claim 1 , wherein the annealing of the wafer is performed at a temperature of 800° C. to 1800° C. 3. The method of claim 1 , wherein the annealing of the wafer is performed for 1 hour or more. 4. The method of claim 1 , wherein the cooling of the wafer comprises: a first cooling of the wafer after the wafer has been grown; and a second cooling of the wafer after the wafer has been annealed. 5. The method of claim 4 , wherein a stepwise cooling is performed in the second cooling of the wafer. 6. A method of fabricating a wafer, the method comprising: growing a single crystal layer on a surface of the wafer at a growth temperature; annealing the wafer after the single crystal layer has been grown; and cooling the wafer after the wafer has been annealed, wherein the annealing of the wafer is performed at a temperature higher than the growth temperature, wherein the growing of the single crystal layer and the annealing of the wafer are performed in the same chamber in situ, and wherein the wafer is cut at an angle of 4° or 8°. 7. The method of claim 6 , wherein the annealing of the wafer is performed at a temperature higher than the growth temperature by 100° C. to 200° C. 8. The method of claim 6 , wherein the cooling of the wafer comprises cooling the wafer until a first temperature is reached, maintaining the wafer at the first temperature, cooling the wafer until a second temperature lower than the first temperature is reached, maintaining the wafer at the second temperature, cooling the wafer until a third temperature lower than the second temperature is reached, maintaining the wafer at the third temperature, cooling the wafer until a fourth temperature lower than the third temperature is reached, and maintaining the wafer at the fourth temperature. 9. The method of claim 8 , wherein the fourth temperature corresponds to the growth temperature. 10. The method of claim 6 , wherein a stepwise cooling is performed in the cooling of the wafer until a temperature becomes equal to or lower than the growth temperature. 11. The method of claim 8 , wherein the cooling of the wafer further comprises cooling the wafer until a fifth temperature lower than the fourth temperature is reached, maintaining the wafer at the fifth temperature, cooling the wafer until a sixth temperature lower than the fifth temperature is reached, and maintaining the wafer at the sixth temperature. 12. The method of claim 6 , wherein the annealing of the wafer is performed at a temperature of 800° C. to 1800° C. 13. The method of claim 1 , wherein the wafer includes silicon carbide. 14. The method of claim 1 , wherein the annealing is performed under a vacuum condition. 15. The method of claim 11 , wherein the stepwise cooling is performed at a rate of 0.1° C./hour to 10° C./hour. 16. The method of claim 6 , wherein the wafer includes silicon carbide. 17. The method of claim 6 , wherein the annealing is performed under a vacuum condition. 18. The method of claim 10 , wherein the stepwise cooling is performed at a rate of 0.1° C./hour to 10° C./hour.

Assignees

Inventors

Classifications

  • Thermal treatments, e.g. annealing or sintering · CPC title

  • Silicon, silicon germanium or germanium · CPC title

  • Crystal orientations · CPC title

  • Silicon carbide · CPC title

  • characterised by treatments done after the formation of the materials · CPC title

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Frequently asked questions

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What does patent US9745667B2 cover?
A method of fabricating a wafer according to the embodiment comprises the steps of growing an wafer on a surface of the wafer in a growth temperature; and cooling the wafer after the wafer has been grown, wherein a stepwise cooling is performed when cooling the wafer.
Who is the assignee on this patent?
Kang Seok Min, Kim Moo Seong, Lg Innotek Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/2904. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 29 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).