Layered coatings for sapphire substrate

US9745662B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9745662-B2
Application numberUS-201414214163-A
CountryUS
Kind codeB2
Filing dateMar 14, 2014
Priority dateMar 15, 2013
Publication dateAug 29, 2017
Grant dateAug 29, 2017

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  1. Title

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  5. First independent claim

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Abstract

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A layered coating for a sapphire component is described herein. The sapphire component comprises one or more layers of alumina adhered to the surface of a sapphire member. At least the first layer of alumina adheres to the surface of the sapphire member filling all defects in the surface forming a pristine new layer that also provides isolation from damage.

First claim

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We claim: 1. An electronic device, comprising: a window, comprising: a sapphire substrate comprising a first surface and a second surface each having an array of surface defects, the second surface positioned opposite the first surface; a first layer adhered to the first surface and the array of surface defects on the first surface to fill the surface defects, the first layer formed of one of alumina or silicon oxynitride at a first thickness; and a second layer adhered to the second surface and the array of surface defects on the second surface, the second layer formed from one of alumina or silicon oxynitride at a second thickness that is less than the first thickness, wherein the second layer induces a compressive stress within the sapphire substrate. 2. The electronic device of claim 1 wherein the second layer is formed at an elevated temperature and cooled to produce the compressive stress within the sapphire substrate. 3. The electronic device of claim 1 further comprising: an additional layer adhered to the first layer, wherein the additional layer is formed from the same chemical composition as the first layer but has a different structure than the first layer, the different structure causing the additional layer to have a different physical characteristic. 4. The electronic device of claim 1 , wherein the first layer has a hardness lower than the sapphire substrate, and wherein the hardness of the first layer is 7 to 9 on the Mohs scale. 5. The electronic device of claim 3 , wherein the additional layer is alumina and the alumina of the additional layer has a hardness between the hardness of the sapphire and the hardness of the first layer. 6. The electronic device of claim 3 , wherein the additional layer is one of silicone oxynitride or alumina and is softer than the first layer. 7. The electronic device of claim 3 , wherein: the additional layer comprises a polymer matrix having a plurality of blocks suspended within the polymer matrix; and the plurality of blocks are configured to deflect into the depth of the polymer matrix when a force is exerted thereon. 8. The electronic device of claim 3 , wherein the additional layer is an anti-reflective coating having a refractive index less than the first layer. 9. The electronic device of claim 1 , wherein: one of at least the first surface or second surface is an amorphous surface; and the amorphous surface is ion-implanted. 10. An electronic device, comprising: a housing; and a sapphire structure coupled to the housing, comprising: a sapphire layer having an array of surface defects; and first and second layers directly bonded to opposing surfaces of the sapphire structure to fill the surface defects and having distinct thicknesses, wherein: at least one of the first and second layers induces a compressive stress within the sapphire structure. 11. The electronic device of claim 10 , wherein the first and second layers are formed from one of alumina or silicon oxynitride. 12. The electronic device of claim 10 , wherein the sapphire structure has a refractive index that is distinct from a refractive index of the first and second layers. 13. The electronic device of claim 10 , where the sapphire structure forms an exterior surface of the electronic device. 14. The electronic device of claim 10 , wherein: the second layer induces the compressive stress; and the second layer has a thickness that is less than a thickness of the first layer. 15. The electronic device of claim 10 , wherein the first layer has a hardness that is distinct from a hardness of the second layer. 16. An electronic device, comprising: a first sheet defined by a sapphire structure having first and second surfaces with an array of surface defects; a first layer positioned on the first surface and over the surface defects; and a second layer positioned on the second surface and over the surface defects, wherein: the first and second layers are formed from one of alumina or silicon oxynitride; and the second layer induces a compressive stress within the first sheet. 17. The electronic device of claim 16 , wherein the second layer has a thickness that is less than a thickness of the first layer. 18. The electronic device of claim 16 , further comprising: an additional layer adhered to the first layer and forming an anti-reflective coating having a refractive index that is less than the first layer. 19. The electronic device of claim 18 , wherein a difference between a refractive index of the additional layer and a refractive index of the first sheet is greater than: a difference between a refractive index of the first layer and the refractive index of the first sheet; and a difference between the refractive index of the first layer and the refractive index of the additional layer.

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What does patent US9745662B2 cover?
A layered coating for a sapphire component is described herein. The sapphire component comprises one or more layers of alumina adhered to the surface of a sapphire member. At least the first layer of alumina adheres to the surface of the sapphire member filling all defects in the surface forming a pristine new layer that also provides isolation from damage.
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification C23C14/0676. Mapped technology areas include Chemistry & Metallurgy.
When was this patent published?
Publication date Tue Aug 29 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).