Method for manufacturing circuit board

Patent metadata

Field	Value
Publication number	US-9744624-B2
Application number	US-201514742070-A
Country	US
Kind code	B2
Filing date	Jun 17, 2015
Priority date	Jun 17, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 μm for fine line width/pitch.

First claim

What is claimed is:

1. A method for manufacturing a circuit board, comprising:
preparing a substrate covered by a stop layer having a pattern, the stop layer covered by a resin layer, part of the substrate is in contact with the resin layer, the stop layer formed of a metal or an alloy;
forming at least one conduction hole penetrating the resin layer by a laser drilling process or a mechanical drilling process, the at least one conduction hole not entering the stop layer but stopping at a surface of the stop layer so as to expose part of the stop layer via the at least one conduction hole, the at least one hole being a blind hole;
forming a first metal layer on the resin layer and the exposed stop layer through a sputtering process;
forming a second metal layer on the first metal layer through a chemical plating process or an electroless plating process;
forming a third metal layer on the second metal layer through an electroplating process, the third metal layer having a circuit pattern exposing part of the second metal layer and filling up the at least one conduction hole so as to electrically connect the first, second and third metal layers; and
etching the exposed second metal layer and the first metal layer under the exposed second metal layer to expose the resin layer under the first metal layer so as to finish the circuit board.

2. The method as claimed in claim 1 , wherein the at least one conduction hole is formed directly by the laser drilling process using a laser beam.

3. The method as claimed in claim 1 , wherein the at least one conduction hole is formed by first forming a resist layer with a specific pattern on the resin layer, and then using the resist layer as a mask for performing the laser drilling process using a means of laser etching.

4. The method as claimed in claim 1 , wherein an upper surface of the resin layer is covered with a copper layer before forming the at least one conduction hole, the copper layer is treated by a pretreatment process comprising a black process or a brown process for oxidizing a surface of the copper layer, and a laser etching process is performed to form the at least one conduction hole.

5. The method as claimed in claim 1 , wherein the resin layer is formed of a resin base material comprising epoxy resin, FR4, FR5, modified FR4 silicon, BT resin, polyphenylene oxide (PPO), polyimide (PI), Ajinomoto build-up film (ABF), polypropylene (PP) or photo imageable dielectric material (PIDM), and the upper surface of the resin layer has a roughness specified by Ra=0-1 μm and Rz=−10 μm.

6. The method as claimed in claim 1 , wherein an upper surface and/or a lower surface of the substrate is embedded with an inner circuit layer.

7. The method as claimed in claim 6 , wherein the first metal layer comprises an upper metal layer and a lower metal layer, the upper metal layer is stacked on the lower metal layer, the lower metal layer is stacked on the exposed inner circuit layer, the upper metal layer comprises copper (Cu), the lower metal layer comprises titanium (Ti), chromium (Cr) or tantalum (Ta), and the second and third metal layers comprise copper.

8. The method as claimed in claim 7 , wherein the first metal layer further comprises a bottom metal layer provided under the lower metal layer and being in contact with the exposed inner circuit layer, and the bottom metal layer comprises titanium nitride (TiN).

9. The method as claimed in claim 5 , wherein the resin layer further comprises a reinforcing material uniformly dispersed in the resin base material, and the reinforcing material comprises glass fiber or carbon fiber.

10. A method for manufacturing a circuit board, comprising:
preparing a substrate having an upper surface and a lower surface covered by resin layers, respectively;
forming at least one conduction hole by a laser drilling process or a mechanical drilling process, the at least one conduction hole being a through-hole penetrating the substrate and the resin layers covering the upper and lower surfaces of the substrate;
forming a first metal layer on the resin layer through a sputtering process;
forming a second metal layer on the first metal layer through a chemical plating process or an electroless plating process;
forming a third metal layer on the second metal layer through an electroplating process, the third metal layer having a circuit pattern exposing part of the second metal layer and filling up the at least one conduction hole so as to electrically connect the first, second and third metal layers; and
etching the exposed second metal layer and the first metal layer under the exposed second metal layer to expose the resin layer under the first metal layer so as to finish the circuit board.

11. The method as claimed in claim 10 , wherein the at least one conduction hole is formed directly by the laser drilling process using a laser beam.

12. The method as claimed in claim 10 , wherein the at least one conduction hole is formed by first forming a resist layer with a specific pattern on the resin layer, and then using the resist layer as a mask for performing the laser drilling process using a means of laser etching.

13. The method as claimed in claim 10 , wherein an upper surface of the resin layer is covered with a copper layer before forming the at least one conduction hole, the copper layer is treated by a pretreatment process comprising a black process or a brown process for oxidizing a surface of the copper layer, and a laser etching process is performed to form the at least one conduction hole.

14. The method as claimed in claim 10 , wherein the resin layer is formed of a resin base material comprising epoxy resin, FR4, FR5, modified FR4 silicon, BT resin, PPO, PI, ABF, PP or PIDM, and the upper surface of the resin layer has a roughness specified by Ra=0-1 μm and Rz=−10 μm.

15. The method as claimed in claim 10 , wherein an upper surface and/or a lower surface of the substrate is embedded with an inner circuit layer.

16. The method as claimed in claim 15 , wherein the first metal layer comprises an upper metal layer and a lower metal layer, the upper metal layer is stacked on the lower metal layer, the lower metal layer is stacked on the exposed inner circuit layer, the upper metal layer comprises copper, the lower metal layer comprises titanium, chromium or tantalum, and the second and third metal layers comprise copper.

17. The method as claimed in claim 16 , wherein the first metal layer further comprises a bottom metal layer provided under the lower metal layer and being in contact with the exposed inner circuit layer, and the bottom metal layer comprises titanium nitride.

18. The method as claimed in claim 10 , wherein the resin layer further comprises a reinforcing material uniformly dispersed in the resin base material, and the reinforcing material comprises glass fiber or carbon fiber.

Assignees

• Kinsus Interconnect Tech Corp

Inventors

• Lan Jaen-Don
• Lin Pin-Chung
• Tseng Chen-Rui
• Ho Cheng-En
• Chen Yu-An

Classifications

• B23K2203/50

  Operations & Transport · mapped topic

• B23K26/389

  of fluid openings, e.g. nozzles, jets · CPC title

• H05K2201/0341

  Intermediate metal, e.g. before reinforcing of conductors by plating · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• B23K26/402 Primary

  involving non-metallic material, e.g. isolators · CPC title