Relay device and connector

Patent metadata

Field	Value
Publication number	US-9742695-B2
Application number	US-201314076740-A
Country	US
Kind code	B2
Filing date	Nov 11, 2013
Priority date	May 11, 2011
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

To provide a relay device capable of increasing the number of connected nodes in a bus-type network, and a connector providing the relay device. An active-star coupler as the relay device includes a bit width distortion correction circuit and a ringing pulse absorption circuit, corrects bit width distortion in bit units using the bit width distortion correction circuit and absorbs and eliminates ringing pulses in a terminus of a communication frame using the ringing pulse absorption circuit.

First claim

What is claimed is:

1. A relay device for receiving an input signal including a communication frame comprising a signal indicating a head of data, a plurality of bits of data, and a signal indicating a terminus of data by an input channel, and for processing the input signal to transmit an output signal from an output channel, the relay device comprising:
a clock circuit configured to generate a clock signal having a frequency higher than that of the input signal and provide the clock signal to a bit width distortion correction circuit and a ringing pulse absorption circuit;
the bit width distortion correction circuit performing bit width distortion correction processing on the input signal for each bit of the plurality of bits of data; and
the ringing pulse absorption circuit performing ringing pulse elimination processing on the input signal corrected in the bit width distortion circuit by a ringing pulse elimination portion to eliminate ringing pulses present in the input signal after the terminus of data,
wherein the bit width distortion correction circuit detects the signal indicating the head of data and generates a sampling signal using the clock signal provided from the clock circuit to sample the plurality of bits of data according to the signal indicating the head of data as a reference,
wherein the ringing pulse absorption circuit fixes a signal level of signals continued to the signal indicating the terminus of data to a predetermined level when the ringing pulse absorption circuit detects the signal indicating the terminus of data, the predetermined level indicating an idle state, and
wherein an output signal from the ringing pulse absorption circuit is transmitted to the output channel.

2. The relay device according to claim 1 , wherein the bit width distortion correction circuit samples at a center of each bit of the plurality of bits of data.

3. The relay device according to claim 1 , wherein the sampling signal has lower frequency than frequency of the clock circuit.

4. A connector comprising:
a relay device for receiving an input signal including a communication frame comprising a signal indicating a head of data, a plurality of bits of data, and a signal indicating a terminus of data by an input channel, and for processing the input signal to transmit an output signal from an output channel, the relay device comprising:
a clock circuit configured to generate a clock signal having a frequency higher than that of the input signal and provide the clock signal to a bit width distortion correction circuit and a ringing pulse absorption circuit;
the bit width distortion correction circuit performing bit width distortion correction processing on the input signal for each bit of the plurality of bits of data; and
the ringing pulse absorption circuit performing ringing pulse elimination processing on the input signal corrected in the bit width distortion circuit by a ringing pulse elimination portion to eliminate ringing pulses present in the input signal after the terminus of data,
wherein the bit width distortion correction circuit detects the signal indicating the head of data and generates a sampling signal using the clock signal provided from the clock circuit to sample the plurality of bits of data according to the signal indicating the head of data as a reference,
wherein the ringing pulse absorption circuit fixes a signal level of signals continued to the signal indicating the terminus of data to a predetermined level when the ringing pulse absorption circuit detects the signal indicating the terminus of data, the predetermined level indicating an idle state,

wherein an output signal from the ringing pulse absorption circuit is transmitted to the output channel, and
a connection portion is electrically coupled to the relay device, wherein the connection portion engages with a mating connector.

5. The connector according to claim 4 ,
wherein the bit width distortion correction circuit samples at a center of each bit of the plurality of bits of data.

6. The connector according to claim 4 , wherein the sampling signal has lower frequency than frequency of the clock circuit.

7. A network system comprising:
an active coupler for receiving an input signal including a communication frame comprising a signal indicating a head of data, a plurality of bits of data, and a signal indicating a terminus of data by an input channel and for processing the input signal to transmit an output signal from an output channel, the active coupler comprising:
a clock circuit configured to generate a clock signal having a frequency higher than that of the input signal and provide the clock signal to a bit width distortion correction circuit and a ringing pulse absorption circuit;
the bit width distortion correction circuit performing bit width distortion correction processing on the input signal for each bit of the plurality of bits of data; and
the ringing pulse absorption circuit performing ringing pulse elimination processing on the input signal corrected in the bit width distortion circuit by a ringing pulse elimination portion to eliminate ringing pulses present in the input signal after the terminus of data,
wherein the bit width distortion correction circuit detects the signal indicating the head of data and generates a sampling signal using the clock signal provided from the clock circuit to sample the plurality of bits of data according to the signal indicating the head of data as a reference,
wherein the ringing pulse absorption circuit fixes a signal level of signals continued to the signal indicating the terminus of data to a predetermined level when the ringing pulse absorption circuit detects the signal indicating the terminus of data, the predetermined level indicating an idle state, and
wherein an output signal from the ringing pulse absorption circuit is transmitted to the output channel;

a plurality of nodes; and
at least two passive couplers, wherein the passive couplers are connected to the plurality of nodes,
wherein the active coupler is inserted between the passive couplers.

Assignees

• Yazaki Corp

Inventors

• YANAGIDA You
• Hamaguchi Hiroki

Classifications

• H04L25/03878 Primary

  Line equalisers; line build-out devices · CPC title

• H04L25/245

  for start-stop signals (detection of start or stop bits H04J3/0602) · CPC title

• H04L49/15 Primary

  Interconnection of switching modules · CPC title