Method of dynamically renumbering ports and an apparatus thereof

Patent metadata

Field	Value
Publication number	US-9742694-B2
Application number	US-201414309789-A
Country	US
Kind code	B2
Filing date	Jun 19, 2014
Priority date	Jun 19, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total amount of state space required for the ports on the network chip.

First claim

We claim:

1. A method of a network chip including N ports and P pipes,
the method comprising:
receiving traffic; and
utilizing a dynamic port renumbering scheme by each of the P pipes to renumber each of the N ports associated with that pipe such that hardware implemented on the network chip to preserve state information for the N ports is limited, wherein each of the P pipes handles traffic from M ports of the N ports, wherein M is the ceiling of N/P.

2. A method of a network chip including N ports and P pipes,
the method comprising:
receiving traffic; and
utilizing a dynamic port renumbering scheme by each of the P pipes to renumber each of the N ports associated with that pipe such that hardware implemented on the network chip to preserve state information for the N ports is limited, wherein each of the P pipes uses M relative port numbers in the dynamic port renumbering scheme, wherein M is the ceiling of N/P.

3. A method of a network chip including N ports and P pipes, the method comprising:
receiving traffic; and
utilizing a dynamic port renumbering scheme by each of the P pipes to renumber each of the N ports associated with that pipe such that hardware implemented on the network chip to preserve state information for the N ports is limited, wherein utilizing a dynamic port renumber scheme includes, for each of the P pipes:
assigning one of M relative port numbers to each of M ports associated with that pipe, wherein M is the ceiling of N/P;
storing all of the assignments of relative port numbers to the M ports; and
maintaining all states of the M ports using the M relative port numbers.

4. The method of claim 3 , wherein assigning one of M relative port numbers includes:
determining whether renumbering of one of the M ports is completed;
based on the determination that the renumbering of that port is completed, using the relative port number previously assigned to that port; and
based on the determination that the renumbering of that port is not completed, assigning an unused relative port number of the M relative port numbers to that port.

5. The method of claim 1 , wherein the dynamic port renumbering scheme is a self-learning scheme.

6. A method of a network chip including N ports and P pipes, the method comprising:
for each one of the P pipes:
handling traffic from a subset of M ports of the N ports, wherein M is the ceiling of N/P;
assigning a different one of M relative port numbers to each of the M ports, wherein the M relative port numbers are associated with the one of the P pipes; and
maintaining state space for the one of the P pipes for the M relative port numbers.

7. The method of claim 6 , wherein the one of the M relative port numbers has not yet been used prior to the assignment.

8. The method of claim 6 , wherein assigning one of M relative port numbers to each of the M ports includes:
receiving traffic;
identifying one of the M ports that the traffic is from; and
determining whether that port had previously been assigned a relative port number.

9. The method of claim 8 , further comprising, based on the determination that that port has not yet been assigned a relative port number, assigning an unused relative port number of the M relative port numbers to that port.

10. The method of claim 6 , further comprising:
storing all of the assignments of the M relative port numbers to the M ports; and
maintaining all states of the M ports using the M relative port numbers.

11. A network chip comprising:
N ports;
P pipes to handle traffic from the N ports; and
a dynamic port renumbering scheme utilized by each of the P pipes to renumber each of the N ports associated with that pipe, wherein hardware implemented on the network chip to preserve state information for the N ports is limited, and further wherein each of the P pipes handles traffic from M ports of the N ports, wherein M is the ceiling of N/P.

12. A network chip comprising:
N ports;
P pipes to handle traffic from the N ports; and
a dynamic port renumbering scheme utilized by each of the P pipes to renumber each of the N ports associated with that pipe, wherein hardware implemented on the network chip to preserve state information for the N ports is limited, and further wherein each of the P pipes uses M relative port numbers in the dynamic port renumbering scheme, wherein M is the ceiling of N/P.

13. A network chip comprising:
N ports;
P pipes to handle traffic from the N ports; and
a dynamic port renumbering scheme utilized by each of the P pipes to renumber each of the N ports associated with that pipe, wherein hardware implemented on the network chip to preserve state information for the N ports is limited, wherein the dynamic port renumbering scheme, for each of the P pipes:
assigns one of M relative port numbers to each of M ports associated with that pipe, wherein M is the ceiling of N/P;
stores all of the assignments of relative port numbers to the M ports; and
maintains all states of the M ports using the M relative port numbers.

14. The network chip of claim 13 , wherein one of M relative port numbers is assigned based on whether renumbering of one of the M ports that incoming traffic is from is completed.

15. The network chip of claim 14 , wherein based on the renumbering of that port being completed, the relative port number previously assigned to that port is used.

16. The network chip of claim 14 , wherein based on the renumbering of that port being not completed, an unused relative port number of the M relative port numbers is assigned to that port.

17. A network chip comprising:
N ports; and
P pipes, wherein each of the P pipes:
handles traffic from a subset of M ports of the N ports, wherein M is the ceiling of N/P;
assigns a different one of M relative port numbers to each of the M ports, wherein the M relative port numbers are associated with the one of the P pipes; and
maintains state space for the one of the P pipes for the M relative port numbers.

18. The method of claim 17 , wherein the one of the M relative port numbers has not yet been used prior to the assignment.

19. The network chip of claim 17 , wherein each of the P pipes further:
receives traffic;
identifies one of the M ports that the traffic is from; and
determines whether that port had previously been assigned a relative port number.

20. The method of claim 19 , further comprising, based on the determination that that port has not yet been assigned a relative port number, the pipe assigns an unused relative port number of the M relative port numbers to that port.

21. The method of claim 17 , wherein each of the P pipes further stores all of the assignments of the M relative port numbers to the M ports and maintains all states of the M ports using the M relative port numbers.

22. A network switch comprising:
a plurality of switch ports; and
at least one network chip including N chip ports and P pipes, wherein the N chip ports are mapped to the plurality of switch ports, and wherein the P pipes utilize a dynamic port renumbering scheme to renumber each of the N ports associated with that pipe to a relative port number associated with that pipe, wherein each of the P pipes handles traffic from M ports of the N chip ports, wherein M is the ceiling of N/P.

23. The network switch of claim 22 , wherein the dynamic port renumbering scheme is implemented by each of the P pipes.

24. The network switch of claim 22 , wh

Assignees

• Cavium Inc

Inventors

• Anand Vishal
• Panchagnula Vamsi

Classifications

• H04L49/109 Primary

  Integrated on microchip, e.g. switch-on-chip · CPC title

• G06F8/314

  Parallel programming languages (G06F8/313 takes precedence) · CPC title

• H04L69/329

  in the application layer [OSI layer 7] · CPC title

• H04L29/08072

  Electricity · mapped topic

• H04L29/06

  Electricity · mapped topic