Configurable router for a network on chip (NoC)

Patent metadata

Field	Value
Publication number	US-9742630-B2
Application number	US-201414493018-A
Country	US
Kind code	B2
Filing date	Sep 22, 2014
Priority date	Sep 22, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Example implementations described herein are directed to a configurable building block, such as a router, for implementation of a Network on Chip (NoC). The router is parameterized by a software layer, which can include the number of virtual channels for a port, the number of ports, the membership information of the virtual channels, clock domain, and so forth. The router may further be configured to implement arbitration techniques and flit processing techniques based on the parameters specified by the software layer.

First claim

What is claimed is:

1. A router in a Network on Chip (NoC) comprising a plurality of routers, the router comprising:
a plurality of ports, each of the plurality of ports configured with one or more virtual channels (VCs), each of the one or more VCs associated with a separate buffer, each of the one or more VCs configured to connect to specified one or more other ports or VCs of the plurality of ports based on a membership specified by a specification;
wherein a number of the plurality of ports and a number of the one or more VCs for the each of the plurality of ports is specified by the specification;
wherein a size of each of the one or more VCs and a size of the buffer is specified by the specification;
wherein the connectivity between each of the one or more VCs is specified by the specification;
wherein the one or more VCs are configured to operate in different clock domain as specified by the specification;

wherein said NoC is constructed by a software layer that configures the one or more of the plurality of routers with information from the specification and connects one or more of the plurality of ports of the one or more of the plurality of routers to one another or to one or more agents of the NoC, and that further configures the one or more of the plurality of routers with information to facilitate routing of packets between NoC agents.

2. The router of claim 1 , further comprising a controller, wherein the controller is configured to upsize or downsize a flit received at an input one of the one or more VCs and directed to an output one of the one or more VCs based on a size ratio of the input one of the one or more VCs and the output one of the one or more VCs.

3. The router of claim 1 , wherein the router is configured to
receive a packet at one of the one or more input VCs of one of the one or more input ports comprising a first set having first information for arbitration of the packet and second information for routing of the packet;
arbitrate the packet and upon winning the arbitration, perform output VC and output port selection of one of the plurality of output VCs and output ports from the first information;
calculate a second set having first information and second information for arbitration and routing of the packet at next NoC router using the first and second information; and
forward the second set along with the packet to the next NoC router.

4. The router of claim 3 , wherein the first information of the packet is indicative of the output VC and output port at a router and second information of the packet is indicative of one or more turns at one or more routers of the NoC.

5. The router of claim 1 , wherein each of the one or more VCs is associated with a Quality of Service (QoS) specified by the specification, wherein the router is configured to conduct arbitration based on the QoS of the one or more VCs.

6. The router of claim 1 , wherein each of the one or more VCs is associated with a clock domain specified by the specification, and wherein the router is configured to facilitate clock domain crossing logic for the one or more VCs.

7. The router of claim 1 , wherein the router is configured to facilitate independent flow control for each one of the plurality of ports that is connected to another router port or an agent of the NoC.

8. The router of claim 7 , wherein the router is configured with flow control information from the specification to facilitate the independent flow control between each one of the plurality of ports of the router and the corresponding another router port or NoC agent connected to the port.

9. The router of claim 1 , wherein the router further comprises an output buffering stage for one or more of the plurality of ports specified by the specification.

10. The router of claim 1 , wherein the router further comprises a pipeline with one or more stages for one or more of the plurality of ports, the one or more stages and the one or more of the plurality of ports specified by the specification.

11. The router of claim 1 , wherein the router is configured to, for each arbitration operation:
transmit a number of flits from the one or more input VCs of ones of the plurality of input ports to one or more output VCs of ones of the plurality of output ports; the number of flits specified by the specification.

12. A semiconductor device configured with a Network on Chip (NoC) generated from a specification, the semiconductor device comprising:
one or more hosts; and
a router, comprising:
a plurality of ports, each of the plurality of ports configured with one or more virtual channels (VCs), each of the one or more VCs associated with a separate buffer, each of the one or more VCs configured to connect to specified one or more other ports or VCs of the plurality of ports based on a membership specified by the specification;
wherein a number of the plurality of ports and a number of the one or more VCs for the each of the plurality of ports is specified by the specification;
wherein a size of each of the one or more VCs and a size of the buffer is specified by the specification;
wherein the connectivity between each of the one or more VCs is specified by the specification;
wherein the one or more VCs are configured to operate in different clock domain as specified by the specification;
wherein said NoC is constructed by a software layer that configures the one or more of the plurality of routers with information from the specification and connects one or more of the plurality of ports of the one or more of the plurality of routers to one another or to one or more agents of the NoC, and that further configures the one or more of the plurality of routers with information to facilitate routing of packets between NoC agents.

13. The semiconductor device of claim 12 , wherein the router comprises a controller, wherein the controller is configured to upsize or downsize a flit received at an input one of the one or more VCs and directed to an output one of the one or more VCs, based on a size ratio of the input one of the one or more VCs and the output one of the one or more VCs.

14. The semiconductor device of claim 12 , wherein the router is configured to:
receive a packet at one of the one or more input VCs of one of the one or more input ports comprising a first set having first information for arbitration of the packet and second information for routing of the packet;
arbitrate the packet and upon winning the arbitration, perform output VC and output port selection of one of the plurality of output VCs and output ports from the first information;
calculate a second set having first information and second information for arbitration and routing of the packet at next NoC router using the first and second information; and
forward the second set along with the packet to the next NoC router.

15. The semiconductor device of claim 14 , wherein the first information of the packet is indicative of the output VC and output port at a router, and wherein the second information of the packet is indicative of one or more turns at one or more routers of the NoC.

16. The semiconductor device of claim 12 , wherein each of the one or more VCs is associated with a Quality of Service (QoS) specified by the specification, wherein the router is configured to conduct arbitration based on the QoS of the one or more VCs.

17. The semiconductor device of claim 12 , wherein each of the one or more VCs is associated with a clock domain specified by the specification, and wherein the router is configured to facilitate clock domain crossi

Assignees

• Netspeed Systems

Inventors

• Philip Joji
• Kumar Sailesh

Classifications

• H04L41/0889 Primary

  Techniques to speed-up the configuration process · CPC title

• H04L45/302

  Route determination based on requested QoS · CPC title

• H04L49/109

  Integrated on microchip, e.g. switch-on-chip · CPC title

• H04L45/06

  Deflection routing, e.g. hot-potato routing · CPC title

• H04L45/586

  of virtual routers · CPC title