Core voltage reset systems and methods with wide noise margin

Patent metadata

Field	Value
Publication number	US-9742396-B2
Application number	US-201514596068-A
Country	US
Kind code	B2
Filing date	Jan 13, 2015
Priority date	Sep 5, 2012
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Presented systems and methods facilitate efficient reset operation. In one embodiment, a system comprises a core domain portion an I/O domain portion and a core reset I/O by-pass component. The core domain portion is configured to operate at a nominal core domain voltage level. The I/O domain portion configured to operate at a nominal I/O domain voltage level. The core reset I/O by-pass component configured to forward a reset indication to the core domain independent of the I/O domain. In one exemplary implementation the core reset I/O by-pass component is operable to receive an input reset indication at a high domain voltage level and to convert the input reset indication to a core reset signal that is less than or substantially equal to the nominal core domain voltage, wherein the high domain is voltage higher than the core domain voltage level.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first N channel transistor comprising: a drain configured to receive an input signal at a first voltage; and a gate coupled to receive a second voltage;
a second N channel transistor comprising: a drain coupled to a source of said first N channel transistor; and a gate coupled to said second voltage, wherein said first voltage is larger than said second voltage, and wherein further the source of said second N channel transistor is operable to output a converted signal that is smaller than or substantially equal to said second voltage.

2. The integrated circuit as described in claim 1 further comprising a level restoration circuit coupled to a source of said second N channel transistor, and operable to generate a restored signal by pulling said converted signal to a full swing of said second voltage.

3. The integrated circuit as described in claim 2 ,
wherein said level restoration circuit comprises a P channel transistor comprising a source connected to said second voltage; a drain coupled to the source of said second N channel transistor through a resistor; and a gate connected to an output of an inverter;
wherein said level restoration circuit is transparent to said input signal; and
wherein further said inverter has an input coupled to said converted signal.

4. The integrated circuit as described in claim 3 further comprising a noise margin amplification circuit, coupled to said source of said second N channel transistor and operable to forward said restored signal as an input to a logic circuit and increase a noise margin of said logic circuit in response to the restored signal, said logic circuit configured to operate at said second voltage.

5. The integrated circuit as described in claim 4 , wherein said noise margin amplification circuit comprises a half-Schmitt trigger circuit having an input connected to the source of said second N channel transistor, and an output connected to said logic circuit, and wherein said noise amplification circuit is operable to increase a Voltage-In-Low (VIL) of said logic circuit in response to said restored signal.

6. The integrated circuit as described in claim 5 , wherein said input signal is a reset indication for resetting said logic circuit.

7. The integrated circuit as described in claim 1 , wherein said first voltage is at least in part based on an Input/Output (I/O) power domain of said integrated circuit; wherein said second voltage is at least in part based on a core power domain of said integrated circuit; and wherein said integrated circuit is independent of circuits in the I/O power domain.

8. The integrated circuit as described in claim 1 , wherein said first N channel transistor is a native thick oxide N channel transistor.

9. A system comprising:
a core domain portion configured to operate at a nominal core domain voltage level;
an I/O domain portion operating at a nominal I/O domain voltage level that is different from said nominal core domain voltage level; and
a core reset I/O by-pass component configured to forward a reset indication to the core domain portion, wherein said core reset I/O by-pass component comprising:
a first N channel transistor comprising: a drain configured to receive a reset signal at a first voltage; and a gate coupled to receive a second voltage; and
a second N channel transistor comprising: a drain coupled to a source of said first N channel transistor; and a gate connected to said second voltage, wherein said first voltage is larger than said second voltage, and wherein further the source of said second N channel transistor is operable to output a converted signal that is smaller than or substantially equal to said second voltage.

10. The system as described in claim 9 , wherein said core reset I/O by-pass component further comprises a level restoration circuit coupled to a source of said second N channel transistor, and operable to generate a restored signal by pulling said converted signal to a full swing of said second voltage.

11. The system as described in claim 10 ,
wherein said level restoration circuit comprises a P channel transistor comprising a source connected to said second voltage; a drain coupled to the source of said second N channel transistor through a resistor; and a gate connected to an output of an inverter;
wherein said level restoration circuit is transparent to said reset signal; and
wherein further said inverter has an input coupled to said converted signal.

12. The system as described in claim 10 , wherein said core reset I/O by-pass component further comprises a noise margin amplification circuit coupled to said source of said second N channel transistor and operable to forward said restored signal as an input to a core domain logic circuit and increase a noise margin of said core domain logic circuit in response to the restored signal.

13. The system as described in claim 12 , wherein said noise margin amplification circuit comprises a half-Schmitt trigger circuit having an input connected to the source of said second N channel transistor, and an output connected to said core domain logic circuit, and wherein said noise amplification circuit is operable to increase a Voltage-In-Low (VIL) of said core domain logic circuit in response to said restored signal.

14. The system as described in claim 9 , wherein said first voltage is substantially equal to said nominal I/O domain voltage level, wherein said second voltage is substantially equal to said nominal core domain voltage level, and wherein said core reset I/O by-pass component is independent of circuits in said I/O domain portion.

15. The system as described in claim 9 , wherein said first N channel transistor is a native thick oxide N channel transistor.

16. A system comprising:
a first N channel transistor comprising: a drain configured to receive an input signal substantially at a first voltage; and a gate coupled to receive a second voltage, wherein said first N channel transistor is a thick oxide N channel transistor; and
a second N channel transistor comprising: a drain coupled to a source of said first N channel transistor; and a gate connected to said second voltage, wherein said first voltage is larger than said second voltage, and wherein further the source of said second N channel transistor is operable to output a converted signal that is smaller than or substantially equal to said second voltage.

17. The system as described in claim 16 , wherein said first voltage is at least in part based on an Input/Output (I/O) power domain of said system, and wherein said second voltage is at least in part based on a core power domain of said system.

18. The system as described in claim 16 further comprising a level restoration circuit coupled to a source of said second N channel transistor, and operable to generate a restored signal by pulling said converted signal to a full swing of said second voltage.

19. The system as described in claim 18 , wherein said level restoration circuit comprises: a P channel transistor comprising a source connected to said second voltage; a drain coupled to the source of said second N channel transistor through a resistor; and a gate connected to an output of an inverter,
wherein said level restoration circuit is transparent to said input signal; and
wherein further said inverter has an input coupled to said converted signal.

20. The integrated circuit as described in claim 19 further comprising a noise margin amplification circuit, coupled to said

Assignees

• Li Alan
• Nvidia Corp

Inventors

• Li Alan

Classifications

• H10W90/00

  Package configurations · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H03K19/018507

  Interface arrangements · CPC title

• H01L2924/00

  Electricity · mapped topic

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title