Semiconductor device outputting reference voltages

Patent metadata

Field	Value
Publication number	US-9742356-B2
Application number	US-201313802945-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Apr 11, 2012
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Power consumption of a signal processing circuit is reduced. Further, power consumption of a semiconductor device including the signal processing circuit is reduced. The signal processing circuit includes a reference voltage generation circuit, a voltage divider circuit, an operational amplifier, a bias circuit for supplying bias current to the operational amplifier, and first and second holding circuits. The first holding circuit is connected between the reference voltage generation circuit and the bias circuit. The second holding circuit is connected between the voltage divider circuit and a non-inverting input terminal of the operational amplifier. Reference voltage from the reference voltage generation circuit and reference voltage from the voltage divider circuit can be held in the first and second holding circuits, respectively, so that the reference voltage generation circuit can stop operating. Thus, power consumption of the reference voltage generation circuit can be reduced.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first circuit electrically connected between a first terminal supplied with first power supply voltage and a second terminal supplied with second power supply voltage, the first circuit configured to output first reference voltage and second reference voltage;
a second circuit electrically connected between the first terminal and the second terminal, the second circuit configured to divide the second reference voltage to output third reference voltage;
a first switch electrically connected between the first terminal and the first circuit and turned on or off in accordance with a first signal;
an operational amplifier whose non-inverting input terminal is supplied with the third reference voltage and whose inverting input terminal is supplied with output voltage;
a third circuit configured to supply bias current to the operational amplifier;
a fourth circuit electrically connected between the first circuit and the third circuit, the fourth circuit configured to hold the first reference voltage in accordance with a second signal; and
a fifth circuit electrically connected between the second circuit and the non-inverting input terminal of the operational amplifier, the fifth circuit configured to hold the third reference voltage in accordance with the second signal,
wherein the fourth circuit comprises a first transistor and a first capacitor,
wherein the fifth circuit comprises a second transistor and a second capacitor,
wherein one of a source and a drain of the first transistor is supplied with the first reference voltage,
wherein the other of the source and the drain of the first transistor is electrically connected to the third circuit and the first capacitor,
wherein one of a source and a drain of the second transistor is supplied with the third reference voltage,
wherein the other of the source and the drain of the second transistor is electrically connected to the operational amplifier and the second capacitor,
wherein each of the first transistor and the second transistor comprises an oxide semiconductor in a channel forming region,
wherein the first circuit comprises a third transistor comprising silicon in a channel forming region,
wherein the operational amplifier comprises a fourth transistor comprising silicon in a channel forming region, and
wherein the first switch is turned off while the operational amplifier operates with the third reference voltage.

2. The semiconductor device according to claim 1 ,
wherein the third circuit is electrically connected between the operational amplifier and the second terminal.

3. The semiconductor device according to claim 1 ,
wherein the third circuit is electrically connected between the operational amplifier and the first terminal.

4. The semiconductor device according to claim 1 ,
wherein each of the first transistor and the second transistor is turned on or off in accordance with the second signal.

5. The semiconductor device according to claim 1 , further comprising a first insulating film over the third transistor and the fourth transistor, wherein the first transistor and the second transistor are provided over the first insulating film.

6. The semiconductor device according to claim 1 , wherein the first switch is a transistor comprising an oxide semiconductor in a channel forming region.

7. A semiconductor device comprising:
a first circuit electrically connected between a first terminal supplied with first power supply voltage and a second terminal supplied with second power supply voltage, the first circuit configured to output first reference voltage and second reference voltage;
a first switch electrically connected between the first terminal and the first circuit and turned on or off in accordance with a first signal;
a second circuit electrically connected between the first terminal and the second terminal, the second circuit configured to divide the second reference voltage to output third reference voltage;
an operational amplifier whose non-inverting input terminal is supplied with the third reference voltage and whose inverting input terminal is supplied with output voltage;
a third circuit electrically connected between the operational amplifier and the first terminal, the third circuit configured to supply bias current to the operational amplifier;
a fourth circuit electrically connected between the operational amplifier and the second terminal, the fourth circuit configured to supply bias current to the operational amplifier;
a fifth circuit electrically connected between the first circuit and the third circuit, the fifth circuit configured to hold the second reference voltage in accordance with a second signal;
a sixth circuit electrically connected between the first circuit and the fourth circuit, the sixth circuit configured to hold the first reference voltage in accordance with the second signal; and
a seventh circuit electrically connected between the second circuit and the non-inverting input terminal of the operational amplifier, the seventh circuit configured to hold the third reference voltage in accordance with the second signal,
wherein the fifth circuit comprises a first transistor and a first capacitor,
wherein the sixth circuit comprises a second transistor and a second capacitor,
wherein the seventh circuit comprises a third transistor and a third capacitor,
wherein one of a source and a drain of the first transistor is supplied with the second reference voltage,
wherein the other of the source and the drain of the first transistor is electrically connected to the third circuit and the first capacitor,
wherein one of a source and a drain of the second transistor is supplied with the first reference voltage,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth circuit and the second capacitor,
wherein one of a source and a drain of the third transistor is supplied with the third reference voltage,
wherein the other of the source and the drain of the third transistor is electrically connected to the operational amplifier and the third capacitor,
wherein each of the first transistor, the second transistor and the third transistor comprises an oxide semiconductor in a channel forming region,
wherein the first circuit comprises a fourth transistor comprising silicon in a channel forming region, and
wherein the operational amplifier comprises a fifth transistor comprising silicon in a channel forming region.

8. The semiconductor device according to claim 7 ,
wherein each of the first transistor, the second transistor and the third transistor is turned on or off in accordance with the second signal.

9. The semiconductor device according to claim 7 , further comprising a first insulating film over the fourth transistor and the fifth transistor, wherein the first transistor, the second transistor and the third transistor are provided over the first insulating film.

10. The semiconductor device according to claim 7 , wherein the first switch is a transistor comprising an oxide semiconductor in a channel forming region.

Assignees

• Semiconductor Energy Lab

Inventors

• Takahashi Kei
• Tanada Yoshifumi

Classifications

• H03F1/0261

  with control of the polarisation voltage or current, e.g. gliding Class A · CPC title

• H03F2203/45506

  the CSC comprising only one switch · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• H03F2203/45244

  the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors · CPC title

• H03F1/342

  in field-effect transistor amplifiers · CPC title