Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit

Patent metadata

Field	Value
Publication number	US-9741918-B2
Application number	US-201414508514-A
Country	US
Kind code	B2
Filing date	Oct 7, 2014
Priority date	Oct 7, 2013
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

First claim

What is claimed is:

1. A planarized integrated circuit on a substrate, comprising: a series of planarized layers comprising at least two layers, formed successively on the substrate, each respective layer comprising: an electrically conductive via layer, patterned into a set of vias which define a set of vertically extending structures which electrically interconnect with conductive structures of an adjacent layer; an electrically conductive layer, formed by deposition over, and adjacent to, the electrically conductive via layer patterned into the set of vias, the electrically conductive layer-being patterned into a set of wires by removal of portions of the electrically conductive layer surrounding the set of wires, with the set of vertically extending structures extending above the set of wires which do not overly the set of vias; a first insulating layer formed over the electrically conductive via layer and the electrically conductive layer which is etched using an anisotropic etch process, to maintain a nonplanar raised Caldera pattern surrounding edges of the set of wires; and a second insulating layer formed over the set of wires and the set of vias, formed over the first insulating layer having the maintained raised Caldera pattern surrounding edges of the set of wires, to produce a conformal coating, which is etched using an anisotropic etch process, to maintain conformally coated raised Caldera pattern surrounding edges of the set of wires, and raised Caldera pattern surrounding edges of the set of vias, the second insulating layer being planarized to expose upper portions of the set of vertically extending structures, and remove the conformally coated raised Caldera pattern surrounding edges of the set of wires and the raised Caldera pattern surrounding edges of the set of vias, wherein the conformally coated raised Caldera pattern is independent of the set of vertically extending structures, wherein the electrically conductive layer, electrically conductive via layer, first insulating layer and second planarized insulating layer being formed as a four layer stack which is planarized once, such that upper portions of the set of vertically extending structures are exposed through the planarized second insulating layer, and wherein the electrically conductive via layer of a respective planarized layer is formed over exposed upper portions of the set of vertically extending structures of a respectively lower planarized layer.

2. The integrated circuit of claim 1 , wherein at least one of the electrically conductive layer and the electrically conductive via layer comprises a niobium-based superconductive material.

3. The integrated circuit of claim 1 , wherein the insulating layer comprises silicon dioxide.

4. The integrated circuit of claim 1 , further comprising at least one non-planarized circuit layer lying above at least one planarized layer.

5. The integrated circuit of claim 1 , further comprising at least one Josephson junction formed within a planarized layer, electrically connected to the set of wires.

6. The integrated circuit of claim 1 , further comprising a single-flux-quantum circuit formed having a Josephson junction within a planarized layer, electrically connected to the set of wires.

7. The integrated circuit of claim 1 , wherein a minimum transverse dimension of a conductive wire is less than 1 micron.

8. The integrated circuit of claim 1 , wherein at least one conductive layer comprises a ground plane.

9. The superconducting integrated circuit of claim 1 , wherein at least 10 planarized layers are present.

10. The planarized integrated circuit of claim 1 , wherein the raised Caldera pattern surrounding edges of the set of vias is formed by a complementary-to-the-metal-mask pattern mask biased for misalignment compensation, and reactive ion etching.

11. The planarized integrated circuit of claim 10 , wherein the electrically conductive layer and the electrically conductive via layer are each formed of a cryogenically superconductive material.

12. A planarized integrated circuit on a substrate, comprising a series of successive planarized sets of layers, at least one planarized set of layers comprising: an electrically conductive via layer patterned into a set of vias having via edges, formed on a planar surface; a patterned electrically conductive layer formed into a set of wires having wire edges, superposed on the patterned electrically conductive via layer, wherein portions where the set of wires which coincide in a plane of the planarized set of layers with the set of vias, define vertically extending conductive structures configured to provide a conductive path between the set of wires of the respective layer and a set of wires of an adjacent layer; a first insulating sublayer conformally surrounding the set of wires and the set of vias, which is anisotropically etched to produce a raised pattern having first protrusions corresponding to the wire edges; and a second insulating sublayer, deposited over the first insulating sublayer, having a raised pattern comprising second protrusions corresponding to the first protrusions, and the set of vias, which is anisotropically etched to produce a modified raised pattern having third protrusions corresponding to the via edges, and the second protrusions, the second insulating sublayer being planarized after the anisotropic etch, such that portions of the vertically extending structures are exposed at an upper surface of the planarized second insulating sublayer, and edges of the planarized second insulating sublayer around the exposed portions of the vertically extending structures, comprise planarized Caldera edges, and portions of the set of wires not superposed on the set of vias are covered by the first insulating sublayer and the second insulating sublayer.

13. The planarized integrated circuit of claim 12 , wherein the electrically conductive via layer of a subsequent planarized set of layers is disposed on a planarized surface of a respective planarized second insulating sublayer of a preceding set of layers, formed by plasma-enhanced, chemical vapor deposition, in electrical contact with the exposed portions of the vertically extending structures of the preceding planarized set of layers.

14. The planarized integrated circuit of claim 12 , wherein the planarized second insulating sublayer has a chemical-mechanical polishing planarized surface.

15. The planarized integrated circuit of claim 12 , comprising at least 8 successive planarized sets of layers.

16. The planarized integrated circuit of claim 12 , wherein at least one of the electrically conductive layer, and the electrically conductive via layer is a sputtered layer.

17. The planarized integrated circuit of claim 12 , wherein at least one of the electrically conductive layer and the electrically conductive via layer has a reactive ion etching-formed pattern.

18. The planarized integrated circuit of claim 12 , further comprising at least one Josephson junction formed within a planarized set of layers, electrically connected to the set of wires.

19. The planarized integrated circuit of claim 12 , wherein the raised pattern having first protrusions is formed by a complementary-to-the-metal-mask pattern mask biased for misalignment compensation, and reactive ion etching.

20. The planarized integrated circuit of claim 19 , wherein the electrically conductive layer and the electrically conductive via layer are each formed of a cryogenically superconductive material, without any intervening layer.

Assignees

• Hypres Inc
• Hypres Inc

Inventors

• Yohannes Daniel
• Kirichenko Alexander F
• Vivalda John
• Hunt Richard

Classifications

• G11C11/44

  using super-conductive elements, e.g. cryotron · CPC title

• H01L39/2493

  Electricity · mapped topic

• H01L39/223 Primary

  Electricity · mapped topic

• H01L39/2406

  Electricity · mapped topic

• H01L39/025

  Electricity · mapped topic