Power delivery network (PDN) design for monolithic three-dimensional (3-D) integrated circuit (IC)

Patent metadata

Field	Value
Publication number	US-9741691-B2
Application number	US-201514698842-A
Country	US
Kind code	B2
Filing date	Apr 29, 2015
Priority date	Apr 29, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Systems and methods relate to power delivery networks (PDNs) for monolithic three-dimensional integrated circuits (3D-ICs). A monolithic 3D-IC includes a first die adjacent to and in contact with power/ground bumps. A second die is stacked on the first die, the second die separated from the power/ground bumps by the first die. One or more bypass power/ground vias and one or more monolithic inter-tier vias (MIVs) are configured to deliver power from the power/ground bumps to the second die.

First claim

What is claimed is:

1. An apparatus for delivering power in a monolithic three-dimensional integrated circuit (3D-IC), comprising:
a first die, with a first side of the first die adjacent to and in contact with power/ground bumps, and a second side of the first die comprising a dielectric layer;
a second die stacked on the first die, with a third side of the second die in contact with the dielectric layer, and the second die separated from the power/ground bumps by the first die;
at least a first bypass power/ground via formed in the first die, the first bypass power/ground via in contact with the power/ground bumps; and
a vertical monolithic inter-tier via (MIV) configured to traverse the dielectric layer and couple the first bypass power/ground via to a power delivery network (PDN) in the second die, a combination of at least the first bypass power/ground via, the MIV, and the PDN in the second die to deliver power from the power/ground bumps to the second die.

2. The apparatus of claim 1 , wherein the first side of the first die is a back side of the first die, the second side of the first die is a face of the first die comprising a metal side of the first die, the third side of the second die is a face of the second die comprising a metal side of the second die, wherein second die is stacked on the first die in a face-to-face configuration.

3. The apparatus of claim 2 , wherein the first die comprises a global power delivery network (PDN) layer formed on the face of the first die.

4. The apparatus of claim 1 , wherein the combination further comprises at least a second bypass power/ground via to couple the MIV to the PDN in the second die.

5. The apparatus of claim 1 , wherein the first side of the first die is a face of the first die comprising a metal side of the first die, the second side of the first die is a back side of the first die, the third side of the second die is a face of the second die comprising a metal side of the second die, wherein the second die is stacked on the first die in a face-to-back configuration.

6. The apparatus of claim 5 , wherein the first die comprises a global power delivery network (PDN) layer formed on the back side of the first die.

Assignees

• Qualcomm Inc

Inventors

• Lim Sung Kyu
• Samadi Kambiz
• Du Yang

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title