Semiconductor component with regions electrically insulated from one another and method for making a semiconductor component

Patent metadata

Field	Value
Publication number	US-9741601-B2
Application number	US-39904609-A
Country	US
Kind code	B2
Filing date	Mar 6, 2009
Priority date	Mar 6, 2008
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Semiconductor component comprising at least two semiconductor regions are disclosed. In one embodiment the semiconductor regions of the semiconductor component are electrically isolated from one another by an insulator, and a deposited, patterned, metallic layer extends over the semiconductor regions and over the insulator.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor component comprising a first semiconductor region and a second semiconductor region;
an insulator configured to electronically isolate the first and second semiconductor regions from one another, the insulator completely penetrating through the semiconductor component in a vertical direction;
a deposited, patterned, metallic layer extending over the first and second semiconductor regions and over the insulator; and
an insulation layer applied on a surface of the second semiconductor region that is lying opposite the deposited, patterned, metallic layer,
wherein the insulation layer encompasses the second semiconductor region such that the insulation layer forms an entire exposed surface of the semiconductor component at the second semiconductor region, and
wherein at least a portion of the first semiconductor region forms an exposed surface of the semiconductor component at the first semiconductor region and opposite the deposited, patterned, metallic layer.

2. The semiconductor device of claim 1 , wherein the first and second semiconductor regions of the semiconductor component have a minimum distance of 10 μm with respect to one another.

3. The semiconductor device of claim 1 , wherein the semiconductor component is thicker than 100 μm.

4. The semiconductor device of claim 1 , wherein the insulator has at least approximately the same coefficient of expansion as the first and second semiconductor regions of the semiconductor component.

5. The semiconductor device of claim 1 , wherein the insulator comprises at least 10% silicon oxide and at least 80% nitride.

6. The semiconductor device of claim 1 , further comprising a basic doping, wherein a semiconductor zone of the complementary type with respect to the basic doping of the semiconductor component is provided in the surface of at least one semiconductor region of the semiconductor component.

7. The semiconductor device of claim 1 , wherein the insulation layer contains silicon oxide or nitride.

8. A method for producing a semiconductor device, comprising:
providing a semiconductor component;
introducing doping regions into the semiconductor component to form first and second semiconductor regions;
etching a deep trench into the semiconductor component, the deep trench separating the first and second semiconductor regions;
filling said trench with an insulator;
applying metal layers and insulation layers on the semiconductor component, at least one of the metal layers extending over the insulator and the first and second semiconductor regions of the semiconductor component;
reducing the thickness of the semiconductor component until the trench with the insulator completely penetrates through the semiconductor component; and
applying an insulation layer on at least one part of the semiconductor component on an underside surface of the semiconductor component after the reduction of the thickness, the insulation layer at least abutting the insulator,
wherein the insulation layer encompasses the second semiconductor region such that the insulation layer forms an entire exposed surface of the semiconductor component at the second semiconductor region, and
wherein at least a portion of the first semiconductor region forms an exposed surface of the semiconductor component at the first semiconductor region.

9. The method of claim 8 , wherein the thickness of the semiconductor component is reduced by grinding an underside surface of the semiconductor component.

10. The method of claim 8 , further comprising applying a semiconductor zone of the complementary type with respect to the semiconductor component on at least one part of the semiconductor component on the underside surface at the second semiconductor region after the reduction of the thickness.

11. The method of claim 8 , wherein the insulation layer abuts a lateral surface of the first insulator.

12. The semiconductor device of claim 1 , wherein the insulation layer abuts a lateral surface of the insulator.

13. The semiconductor device of claim 1 , wherein a device for directly electrically isolated signal transfer is formed in the first semiconductor region of the semiconductor component.

14. The semiconductor device of claim 13 , wherein the device for directly electrically isolated signal transfer is formed as an air-core coil transformer.

15. The semiconductor device of claim 13 , wherein the device for directly electrically isolated signal transfer has a light transmitter and a light receiver, which are designed to transmit and to receive light pulses from one part to another part of the semiconductor component through the insulator.

Assignees

• Feldtkeller Martin
• Wahl Uwe
• Infineon Technologies Austria Ag

Inventors

• Feldtkeller Martin
• Wahl Uwe

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/40

  Leadframes · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title