Methods for manufacturing a spacer with desired profile in an advanced patterning process

Patent metadata

Field	Value
Publication number	US-9741566-B2
Application number	US-201615043183-A
Country	US
Kind code	B2
Filing date	Feb 12, 2016
Priority date	Mar 30, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween and etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer.

First claim

What is claimed is:

1. A method for patterning a spacer layer during a multiple patterning process, comprising:
conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween, wherein the spacer layer is a polysilicon silicon or an amorphous silicon;
etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer by simultaneously supplying an oxygen containing gas and a halogen containing gas; and
simultaneously forming an oxidation layer at corners and sidewalls of the spacer layer to provide the corners of the spacer layer with a substantially sharp right angle.

2. The method of claim 1 , wherein the patterned structure includes an amorphous carbon material.

3. The method of claim 1 , wherein the oxygen containing gas is O 2 .

4. The method of claim 1 , wherein the halogen containing gas is selected from a group consisting of HCl, Cl 2 , HBr, and Br 2 .

5. The method of claim 1 , wherein supplying the oxygen containing gas and the halogen containing gas further comprises:
applying a RF bias power of less than 250 Watts.

6. The method of claim 1 , wherein etching the spacer layer further comprises:
predominately etching a top surface and a bottom surface of the spacer layer while forming an oxidation layer at corners and sidewalls of the spacer layer.

7. The method of claim 1 , further comprising:
continuing etching a first portion of the spacer layer while oxidizing a second portion of the spacer layer until a top surface of the patterned structure is exposed.

8. The method of claim 7 , further comprising:
removing the patterned structure from the substrate.

9. The method of claim 8 , further comprising:
using the etched spacer layer as an etching mask.

10. The method of claim 8 , further comprising:
forming a second group of openings in the etched spacer layer with a dimension less than that of the first group of openings.

11. The method of claim 1 , wherein supplying the oxygen containing and the halogen containing gas further comprises:
supplying the oxygen containing gas and the halogen containing gas at a flow ratio by volume between about 1:40 and about 1:5.

12. The method of claim 1 , further comprising a dielectric layer disposed between the patterned structure and the substrate.

13. The method of claim 12 , wherein the dielectric layer is a silicon oxide layer.

14. A method for patterning a spacer layer during a multiple patterning process, comprising:
performing a patterning process on a spacer layer disposed on a substrate, wherein the spacer layer is conformally formed on an outer surface of a patterned structure formed on a film stack disposed on a substrate, wherein the spacer layer is a polysilicon silicon or an amorphous silicon, wherein the patterning process further comprises:
supplying a gas mixture including at least an oxygen containing gas and a halogen containing gas simultaneously to etch a first portion of the spacer layer while simultaneously oxidation a second portion of the spacer layer to provide corners of the spacer layer with a substantially sharp right angle.

15. The method of claim 14 , where supplying the gas mixture further comprising:
applying an RF bias power of less than 250 Watts in the gas mixture.

16. The method of claim 14 , further comprising:
performing a post etching process to selectively remove the patterned structure from the substrate without damaging the spacer layer remaining on the substrate; and
using the remaining spacer layer as an etching mask.

17. The method of claim 14 , wherein the first portion is a top and bottom surface of the spacer layer and the second portion is a corner or sidewall of the spacer layer.

18. A method for pattering a spacer layer disposed on a substrate, comprising:
supplying a gas mixture including at least an oxygen containing gas and a halogen containing gas simultaneously to etch a spacer layer disposed on a substrate, wherein the spacer layer is an amorphous silicon layer or a polysilicon layer;
applying an RF bias power of less than about 250 Watt; and
predominately etching a top surface and a bottom surface of the spacer layer while forming an oxidation layer at corners and sidewalls of the spacer layer to provide the corners of the spacer layer with a substantially sharp right angle.

Assignees

• Applied Materials Inc

Inventors

• TANG Dai-Wen
• Sun Hui
• Liu Chung
• Schwarz Benjamin

Classifications

• H10P76/4088

  Processes for improving the resolution of the masks · CPC title

• H10P50/696

  Process specially adapted to improve the resolution of the mask · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P50/268

  of silicon-containing layers · CPC title