Reconfigurable multi-stack inductor

Patent metadata

Field	Value
Publication number	US-9741485-B2
Application number	US-201514823113-A
Country	US
Kind code	B2
Filing date	Aug 11, 2015
Priority date	Sep 26, 2013
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating.

First claim

What is claimed is:

1. A method of forming a reconfigurable multi-stack inductor structure within a semiconductor structure having a first and a second metal layer, the method comprising:
forming, within the first metal layer, a first inductor structure;
forming, within the first metal layer, a first ground shielding structure that is electrically isolated from and circumferentially bounds the first inductor structure;
forming, within the second metal layer, a second inductor structure;
electrically coupling the first inductor structure and second inductor structure;
forming, within the second metal layer, a second ground shielding structure that is electrically isolated from and circumferentially bounds the second inductor structure;
electrically grounding the first and the second ground shielding structure to generate a first inductance value;
electrically floating the first and the second ground shielding structure to generate a second inductance value; and
forming, within a third metal layer of the semiconductor structure, a ground plane; and
forming a first switch for electrically coupling the first and the second ground shielding structure to the ground plane.

2. The method of claim 1 , wherein:
closing the first switch electrically grounds the first and the second ground shielding structure to generate the first inductance value; and
opening the first switch electrically floats the first and the second ground shielding structure to generate the second inductance value.

3. The method of claim 1 , further comprising:
forming, within the first metal layer, a third ground shielding structure that is electrically isolated from and circumferentially bounds the first ground shielding structure;
forming, within the second metal layer, a fourth ground shielding structure that is electrically isolated from and circumferentially bounds the second ground shielding structure;
electrically coupling the first and the second ground shielding structure;
electrically coupling the third and the fourth ground shielding structure; and
forming a second switch for coupling the first and the third ground shielding structure.

4. The method of claim 1 , wherein:
closing the first switch electrically grounds the first and the second ground shielding structure; and
closing the second switch electrically couples the first, the second, the third, and fourth ground shielding structure, the closing of the first and the second switch generating a third inductance value.

5. The method of claim 1 , wherein:
the first inductor structure comprises a first electrically conductive spiral track structure having a first outer track; and
the second inductor structure comprises a second electrically conductive spiral track structure having a second outer track.

6. The structure of claim 5 , wherein:
the first ground shielding structure comprises a first spiral electrically conductive track located adjacent the first outer track, the first spiral electrically conductive track and adjacent first outer track electrically isolated by a dielectric material located therebetween; and
the second ground shielding structure comprises a second spiral electrically conductive track located adjacent the second outer track, the second spiral electrically conductive track and adjacent second outer track electrically isolated by a dielectric material located therebetween.

Assignees

• IBM

Inventors

• Sun Pinping
• Pei Chengwen
• Xu Zheng

Classifications

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H01F2027/2809

  on stacked layers · CPC title

• H01L2924/0002

  Electricity · mapped topic

• Y10T29/4902

  Electromagnet, transformer or inductor · CPC title