Semiconductor memory device having dummy word lines and operating method thereof

Patent metadata

Field	Value
Publication number	US-9741408-B2
Application number	US-201514924523-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Mar 27, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A semiconductor memory device includes a memory cell array, and a voltage generator suitable for generating voltages supplied to the memory cell array. The memory cell array includes cell strings each including memory cells extending in a first direction and arranged in a second direction and a third direction; bit lines extending in the second direction and electrically coupled to the cell strings; and word lines extending in the third direction and electrically coupled to corresponding memory cells, wherein the word lines includes dummy word lines. A program voltage is supplied to a program word line that is electrically coupled to a memory cell to be programmed, and a level of a first dummy word line voltage supplied to a parallel dummy word line, which is disposed parallel to the program word line in the first direction is different from a level of a second dummy voltage supplied to a nonparallel dummy word line other than the parallel dummy word line.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array; and
a voltage generator suitable for generating voltages supplied to the memory cell array,
wherein the memory cell array comprises:
cell strings each including a dummy cell and memory cells extending in a first direction and arranged in a second direction and a third direction intersecting with the first direction;
bit lines extending in the second direction and electrically coupled to the cell strings;
word lines extending in the third direction intersecting with the second direction and electrically coupled to corresponding memory cells; and
dummy word lines extending in the third direction and electrically coupled to corresponding dummy cells,
wherein a program voltage is supplied to a selected word line that is electrically coupled to a selected memory cell included in a selected cell string, and
wherein a first dummy word line voltage is supplied to a selected dummy word line that is electrically coupled to a dummy cell included in the selected cell string, a second dummy word line voltage is supplied to an unselected dummy word line that is electrically coupled to a dummy cell included in an unselected cell string, and a level of the second dummy word line voltage is different from a level of the first dummy word line voltage.

2. The semiconductor memory device according to claim 1 , further comprising:
an address decoder suitable for supplying one of the voltages generated from the voltage generator to each of the word lines; and
a control logic suitable for controlling the cell strings, the voltage generator and the address decoder,

wherein the voltages includes the first dummy word line voltage, the second dummy word line voltage and the program voltage, and
wherein a first bit line voltage is supplied to a bit line electrically coupled to the selected cell string, and a second bit line voltage different from the first bit line voltage is supplied to a bit line electrically coupled to the unselected cell string.

3. The semiconductor memory device according to claim 2 , further comprising:
an input/output interface suitable for receiving a command and data and transmitting the command to the control logic;
a data buffer suitable for receiving the data from the input/output interface; and
a page buffer suitable for receiving the data from the data buffer,
wherein the control logic receives an address in which the data is to be stored from the input/output interface or determines the address internally, and transmits the address to the address decoder.

4. The semiconductor memory device according to claim 2 , wherein the selected dummy word line is electrically coupled to the selected cell string and a first unselected cell string next to the selected string in the third direction and the first unselected cell string is supplied with the second bit line voltage from one of the bit lines,
wherein a first current flows through the first unselected cell string when the first dummy word line voltage is supplied to the selected dummy word line and a second current flows through the first unselected cell string when the second dummy word line voltage is supplied to the selected dummy word line, and
wherein a level of the first current is lower than a level of the second current.

5. The semiconductor memory device according to claim 2 , wherein the unselected dummy word line is electrically coupled to a second unselected cell string next to the selected string in the second direction,
wherein a first electric field is applied to each memory cell included in the second unselected cell string when the second dummy word line voltage is supplied to the unselected dummy word line, and a second electric field is applied to each memory cell included in the second unselected cell string when the first dummy word line voltage is supplied to the unselected dummy word line, and
wherein a maximum value of the first electric field is lower than a maximum value of the second electric field.

6. The semiconductor memory device according to claim 2 , wherein the control logic generates a voltage generator control signal, and levels of the first dummy word line voltage and the second dummy word line voltage are determined by a level of the voltage generator control signal.

7. The semiconductor memory device according to claim 2 , wherein the first bit line voltage is lower than the second bit line voltage.

8. A method of driving a semiconductor memory device, the semiconductor memory device with a memory cell array that includes cell strings extending in a first direction and arranged in a second direction and a third direction intersecting with the first direction, the method comprising:
determining levels of a first dummy word line voltage and a second dummy word line voltage;
waiting for a program command to be received from an external; and
determining levels of voltages to be supplied to word lines and dummy word lines included in the memory cell array,
wherein the first dummy word line voltage is supplied to a selected dummy word line corresponding to a selected cell string among the cell strings, a second dummy word line voltage is supplied to unselected dummy word lines corresponding to unselected cell strings among the cell strings, and a level of the second dummy word line voltage is different from a level of the first dummy word line voltage.

9. The method according to claim 8 , wherein the memory cell array further comprises:
bit lines extending in the second direction and electrically coupled to the cell strings;
the word lines extending in the third direction intersecting with the second direction and electrically coupled to corresponding memory cells; and
the dummy word lines extending in the third direction and electrically coupled to corresponding dummy cells.

10. The method according to claim 9 , wherein the determining of the levels of the first dummy word line voltage and the second dummy word line voltage comprises:
measuring a parameter of the memory cell array to determine an option based on the measured parameter; and
determining the levels of the first dummy word line voltage and the second dummy word line voltage based on the option.

11. The method according to claim 9 , further comprising:
after the determining the levels of the voltages to be supplied to the word lines, programming the memory cell array.

12. The method according to claim 8 , wherein the determining the levels of the first dummy word line voltage and the second dummy word line voltage comprises:
requesting an address of a selected word line corresponding to a page containing a memory cell to be programmed;
determining a voltage to be supplied to the selected dummy word line as the first dummy word line voltage, wherein the selected dummy word line is electrically coupled to a dummy cell included in the selected cell string; and
determining a voltage to be supplied to unselected dummy word line as the second dummy word line voltage, wherein the unselected dummy word lines are electrically coupled to dummy cells included in the unselected cell strings.

Assignees

• Sk Hynix Inc

Inventors

• Lee Yeonghun

Classifications

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C8/10

  Decoders · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title