Hardware apparatuses and methods to control cache line coherence

Patent metadata

Field	Value
Publication number	US-9740617-B2
Application number	US-201414581097-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache line, a second set of processor cores that each include a cache to store a copy of the cache line, and cache coherence logic to aggregate in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores and send a consolidated acknowledgment message to the first processor core.

First claim

What is claimed is:

1. A hardware apparatus comprising:
a first processor core with a cache to store a cache line;
a second set of processor cores that each include a cache to store a copy of the cache line; and
cache coherence logic circuit to aggregate in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores and send a consolidated acknowledgment message to the first processor core.

2. The hardware apparatus of claim 1 , wherein the request from the first processor core is to update the copy of the cache line in the cache of each of the second set of processor cores.

3. The hardware apparatus of claim 1 , wherein the request from the first processor core is to invalidate the copy of the cache line in the cache of each of the second set of processor cores.

4. The hardware apparatus of claim 1 , wherein the tag directory comprises:
a first tag directory of a domain that includes the cache of the first processor core and a second tag directory of a domain that includes the caches of the second set of processor cores, wherein the cache coherence logic circuit is to send the consolidated acknowledgment message from the second tag directory to the first processor core.

5. The hardware apparatus of claim 4 , wherein a core valid vector of the second tag directory includes an element for each processor core of the second set of processor cores to indicate its cache includes the copy of the cache line.

6. The hardware apparatus of claim 4 , wherein receipt of the request from the first processor core by the second tag directory is to set the second tag directory into an aggregator mode to allow the cache coherence logic circuit to aggregate the acknowledgment message from each of the second set of processor cores and to send the consolidated acknowledgment message from the second tag directory to the first processor core.

7. The hardware apparatus of claim 4 , further comprising a second level tag directory of a domain that includes at least the first tag directory and the second tag directory, wherein the first tag directory and the second tag directory are first level tag directories, a request from the first processor core to modify all copies of the cache line is to be sent to the second level tag directory, and the second level tag directory is to send the request to all first level tag directories with copies of the cache line.

8. The hardware apparatus of claim 4 , further comprising a second level tag directory of a domain that includes at least the first tag directory and the second tag directory, wherein the first tag directory and the second tag directory are first level tag directories, a request from the first processor core to modify all copies of the cache line is to be sent to the second level tag directory, the second level tag directory is to send the request to all first level tag directories in its domain that have copies of the cache line except the first tag directory, and an order marker is to be sent from the second level tag directory to the first processor core to provide a number of first level tag directories that are to send consolidated acknowledgment messages to the first processor core.

9. A method to control cache line coherence comprising:
storing a cache line in a cache of a first processor core and a copy of the cache line in each respective cache of a second set of processor cores;
aggregating in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores; and
sending a consolidated acknowledgment message to the first processor core.

10. The method of claim 9 , wherein the request from the first processor core updates the copy of the cache line in the cache of each of the second set of processor cores.

11. The method of claim 9 , wherein the request from the first processor core invalidates the copy of the cache line in the cache of each of the second set of processor cores.

12. The method of claim 9 , further comprising providing a first tag directory of a domain that includes the cache of the first processor core and a second tag directory of a domain that includes the caches of the second set of processor cores, wherein the sending comprises sending the consolidated acknowledgment message from the second tag directory to the first processor core.

13. The method of claim 12 , further comprising providing a core valid vector of the second tag directory that includes an element for each processor core of the second set of processor cores to indicate its cache includes the copy of the cache line.

14. The method of claim 12 , further comprising setting the second tag directory into an aggregator mode on receipt of the request from the first processor core by the second tag directory to initiate the aggregation, wherein the sending comprises sending the consolidated acknowledgment message from the second tag directory to the first processor core.

15. The method of claim 12 , further comprising a second level tag directory of a domain that includes at least the first tag directory and the second tag directory, wherein the first tag directory and the second tag directory are first level tag directories, a request from the first processor core to modify all copies of the cache line is sent to the second level tag directory, and the second level tag directory sends the request to all first level tag directories with copies of the cache line.

16. The method of claim 12 , further comprising a second level tag directory of a domain that includes at least the first tag directory and the second tag directory, wherein the first tag directory and the second tag directory are first level tag directories, a request from the first processor core to modify all copies of the cache line is sent to the second level tag directory, the second level tag directory sends the request to all first level tag directories in its domain that have copies of the cache line except the first tag directory, and an order marker is sent from the second level tag directory to the first processor core to provide a number of first level tag directories that are to send consolidated acknowledgment messages to the first processor core.

17. An apparatus comprising:
a set of one or more processors; and
a set of one or more data storage devices that stores code, that when executed by the set of processors causes the set of one or more processors to perform the following:
storing a cache line in a cache of a first processor core and a copy of the cache line in each respective cache of a second set of processor cores;
aggregating in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores; and
sending a consolidated acknowledgment message to the first processor core.

18. The apparatus of claim 17 , wherein the set of data storage devices further stores code, that when executed by the set of processors causes the set of processors to perform the following:
wherein the request from the first processor core updates the copy of the cache line in the cache of each of the second set of processor cores.

19. The apparatus of claim 17 , wherein the set of data stora

Assignees

• Intel Corp

Inventors

• Sury Samantika
• Steely Jr Simon
• Hasenplaugh William
• Emer Joel
• Webb David

Classifications

• G06F2212/283

  Plural cache memories · CPC title

• G06F12/0822

  Copy directories (local copy tags for implementing a bus snooping protocol G06F12/0831) · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title