Systems and methods for serial data transfer margin increase

Patent metadata

Field	Value
Publication number	US-9740580-B2
Application number	US-201514748168-A
Country	US
Kind code	B2
Filing date	Jun 23, 2015
Priority date	Jun 23, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for enhancing margin in a serial data transfer.

First claim

What is claimed is:

1. A serial data processing system, the system comprising:
a first latch operable to repeatedly latch a data input based upon a threshold and a first phase of a clock to yield a first output, wherein repeated sampling and superposition of the data input yields an eye;
a second latch operable to repeatedly latch the data input based upon the threshold and a second phase of the clock to yield a second output; and
a control circuit operable to:
compare corresponding instances of the first output and the second output to yield an error value;
detect a transition of the second output corresponding to an edge of the eye;
before the transition of the second output is detected, repeatedly modify the second phase of the clock using a first modification step calculated based at least in part on the error value and a high gain; and
after the transition of the second output is detected, modify the second phase of the clock using a second modification step calculated based at least in part on the error value and a reduced gain.

2. The system of claim 1 , wherein the control circuit is further operable to:
detect one of a group of predefined patterns in the second output; and
wherein modifying the second phase of the clock is only done upon detection of one of a group of predefined patterns in the second output.

3. The system of claim 2 , wherein the one of the group of predefined patterns has at least three bits corresponding to symbols in the data input.

4. The system of claim 3 , wherein the group of predefined patterns includes: ‘11101’ and ‘00010’.

5. The system of claim 3 , wherein the group of predefined patterns includes: ‘00110’ and ‘11001’.

6. The system of claim 1 , wherein the threshold is variable.

7. The system of claim 6 , wherein the control circuit is further operable to:
modify the first phase of the clock based at least in part on the second phase of the clock to yield a modified first phase;
repeatedly sample the data input at the modified first phase to yield a maximum voltage and a minimum voltage; and
modify the threshold based upon a combination of the maximum voltage and the minimum voltage.

8. The system of claim 1 , wherein the serial data processing system is implemented as part of a serial data receiver.

9. The system of claim 8 , wherein the serial receiver is implemented as part of an integrated circuit.

10. The system of claim 1 , wherein detecting a transition of the second output corresponding to the edge of the eye is done using the difference between an odd eye and an even eye output of the second latch.

11. A serial data processing system, the system comprising:
a first latch operable to repeatedly latch a data input based upon a threshold and a first phase of a clock to yield a first output, wherein repeated sampling of the data input yields an eye;
a second latch operable to repeatedly latch the data input based upon the threshold and a second phase of the clock to yield a second output; and
a control circuit operable to:
compare corresponding instances of the first output and the second output to yield an error value;
detect one of a group of first transition patterns in the second output corresponding to an edge of the eye, wherein the first transition pattern is a two bit pattern;
before detection of the one of the group of the first transition patterns, repeatedly modify the second phase of the clock using a first modification step calculated based at least in part on the error value;
detect one of a group of second transition patterns in the second output corresponding to an edge of the eye, wherein the second transition pattern is at least a three bit pattern; and
after detection of the one of the group of the first transition patterns, modify the second phase of the clock using a second modification step calculated only upon detection of one of the group of second transition patterns.

12. The system of claim 11 , wherein the first modification step is calculated based at least in part on a high gain value.

13. The system of claim 12 , wherein the second modification step is calculated based at least in part on a reduced gain value.

14. The system of claim 11 , wherein the group of first transition patterns includes: ‘10’ and ‘01’.

15. The system of claim 11 , wherein the group of second transition patterns includes: ‘11101’ and ‘00010’.

16. The system of claim 13 , wherein the group of second transition patterns includes: ‘001100’ and ‘11001’.

17. The system of claim 11 , wherein the threshold is variable.

18. The system of claim 17 , wherein the control circuit is further operable to:
modify the first phase of the clock based at least in part on the second phase of the clock to yield a modified first phase;
repeatedly sample the data input at the modified first phase to yield a maximum voltage and a minimum voltage; and
modify the threshold based upon a combination of the maximum voltage and the minimum voltage.

19. The system of claim 11 , wherein the serial data processing system is implemented as part of a serial data receiver, and wherein the serial receiver is implemented as part of an integrated circuit.

20. A method for serial data processing, the method comprising:
receiving a data input that when repeated sampled yields an eye;
using a first latch to repeatedly latch the data input based upon a threshold and a first phase of a clock to yield a first output;
using a second latch to repeatedly latch the data input based upon the threshold and a second phase of the clock to yield a second output;
comparing corresponding instances of the first output and the second output to yield an error value;
detecting a transition of the second output corresponding to an edge of the eye;
before the transition of the second output is detected, repeatedly modifying the second phase of the clock using a first modification step calculated based at least in part on the error value and a high gain; and
after the transition of the second output is detected, modifying the second phase of the clock using a second modification step calculated based at least in part on the error value and a reduced gain.

21. A method for serial data processing, the method comprising:
receiving a data input that when repeated sampled yields an eye;
using a first latch to repeatedly latch the data input based upon a threshold and a first phase of a clock to yield a first output;
using a second latch to repeatedly latch the data input based upon the threshold and a second phase of the clock to yield a second output;
comparing corresponding instances of the first output and the second output to yield an error value;
detecting one of a group of first transition patterns in the second output corresponding to an edge of the eye, wherein the first transition pattern is a two bit pattern;
before detection of the one of the group of the first transition patterns, repeatedly modifying the second phase of the clock using a first modification step calculated based at least in part on the error value;
detecting one of a group of second transition patterns in the second output corresponding to an edge of the eye, wherein the second transition pattern is at least a three bit pattern; and
after detection of the one of the group of the first transition patterns, modifying the second phase of the clock using a second modification step calculated only upon detection of one of the group of second transition patterns.

Assignees

• Avago Technologies General Ip

Inventors

• Mobin Mohammad
• Wilson Bruce A
• Xia Haitao

Classifications

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L25/03146

  with a recursive structure (H04L25/03127 takes precedence) · CPC title

• H04L1/24

  Testing correct operation · CPC title

• G06F11/1604 Primary

  where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware · CPC title

• G06F11/0757

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title