Conflict detection circuit for resolving access conflict to peripheral device by multiple virtual machines

Patent metadata

Field	Value
Publication number	US-9740518-B2
Application number	US-201214422058-A
Country	US
Kind code	B2
Filing date	Sep 12, 2012
Priority date	Sep 12, 2012
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A system-on-chip device comprises a core supporting a first virtual machine image and a virtual machine monitoring unit capable of communicating with the first virtual machine image. A shareable resource is also provided as well as a conflict detection unit capable of communicating with the virtual machine monitoring unit and the first virtual machine image. The conflict detection unit is arranged to detect, when in use, an access conflict caused by more than one virtual machine image attempting to access initially the shareable resource. The conflict detection unit is arranged to refer, when in use, the access conflict in response to detection thereof to the virtual machine monitoring unit for resolving of the access conflict, thereby handling the access conflict before the virtual machine monitoring unit.

First claim

The invention claimed is:

1. A processing device, comprising:
a first processor core supporting a first virtual machine;
a second processor core supporting a second virtual machine;
a hypervisor capable of communicating with the first and second virtual machines;
a peripheral device shareable between the first and second virtual machines through an interface of the peripheral device, the interface comprising a set of registers; and
a conflict detection circuit capable of communicating with the hypervisor and the first and second virtual machines,
wherein the conflict detection circuit is arranged to support a first and a second virtual image of the set of registers, each virtual image containing a set of register images each mapped to corresponding ones of the set of registers, wherein the first virtual image is associated with the first virtual machine and the second virtual image is associated with the second virtual machine,
wherein the conflict detection circuit is arranged to handle an access request to the peripheral device before the hypervisor by:
detecting an access conflict caused by a current write request by the second virtual machine to access a register of the peripheral device via the corresponding register image of the second virtual image, wherein the register was previously being accessed by the first virtual machine; and
referring the access conflict in response to detection thereof to the hypervisor for resolving the access conflict, wherein the hypervisor is bypassed in the absence of the access conflict;

wherein, the hypervisor is configured to merge data of the current write request with data previously stored by the first virtual machine, and to write the merged data to the peripheral device.

2. The processing device of claim 1 , wherein the first virtual machine comprises a first virtual machine image and the second virtual machine comprises a second virtual machine image.

3. The processing device of claim 2 , wherein the second virtual machine is arranged to bypass the hypervisor when attempting initial access of the peripheral device.

4. The processing device of claim 2 , wherein access by the first virtual machine and the second virtual machine to the peripheral device is identifiable to the conflict detection circuit by a first identifier and a second identifier associated with the first virtual machine and the second virtual machine, respectively, as opposed to by an address associated with the peripheral device.

5. The processing device of claim 1 , wherein at least one of the first and second virtual machines is arranged to bypass the hypervisor when attempting initial access of the peripheral device.

6. The processing device of claim 1 , wherein the conflict detection circuit is operably coupled to a memory for storing at least one data bit in response to receipt of an attempt to access the peripheral device, said data bit indicating the access in respect of the peripheral device.

7. The processing device of claim 6 , wherein the conflict detection circuit is arranged to refer to the memory in response to a detection of an attempt to access the peripheral device, in order to determine whether the attempted access constitutes, if permitted, the access conflict in respect of the peripheral device.

8. The processing device of claim 1 , wherein the conflict detection circuit is arranged to generate a trap into the hypervisor in response to a determination that the attempted access constitutes, if permitted, the access conflict.

9. The processing device of claim 1 , wherein the conflict detection circuit is arranged to provide more than one virtual image of the set of registers.

10. The processing device of claim 9 , wherein the access conflict is a conflict in respect of the more than one virtual machine accessing the same register of the peripheral device via different register images.

11. The processing device of claim 1 , wherein a memory operatively coupled to the conflict detection circuit is arranged to store data bits to identify access to the peripheral device via the first and second virtual image.

12. The processing device of claim 1 , wherein the peripheral device comprises a range of addresses of a register and the access conflict is in respect of more than one virtual machine accessing the same range of addresses of the peripheral device.

13. The processing device of claim 1 , wherein the conflict detection circuit to set a bit field in a memory to indicate that the peripheral device is being accessed by the first virtual machine.

14. A method of peripheral access for a plurality of virtual machines, the method comprising:
supporting a first virtual machine on a first processor core;
supporting a second virtual machine on a second processor core;
supporting a hypervisor capable of communicating with the first and second virtual machines;
supporting a peripheral device shareable between the first and second virtual machines through an interface of the peripheral device, the interface comprising a set of registers;
supporting a conflict detection circuit capable of communicating with the hypervisor and the first and second virtual machines,
wherein the conflict detection circuit is arranged to support a first and a second virtual image of the set of registers, each virtual image containing a set of register images each mapped to corresponding ones of the set of registers, wherein the first virtual image is associated with the first virtual machine and the second virtual image is associated with the second virtual machine,
wherein the conflict detection circuit is arranged to handle an access request to the peripheral device before the hypervisor by:
detecting an access conflict caused by a current write request by the second virtual machine to access a register of the peripheral device via the corresponding register image of the second virtual image, wherein the register was previously being accessed by the first virtual machine; and
referring the access conflict in response to detection thereof to the hypervisor for resolving the access conflict, wherein the hypervisor is bypassed in the absence of the access conflict;

wherein, the hypervisor is configured to merge data of the current write request with data previously stored by the first virtual machine, and to write the merged data to the peripheral device.

15. The method of claim 14 , further comprising:
setting a bit field in a memory operably coupled to the conflict detection circuit to indicate that the peripheral device is being accessed by a virtual machine.

16. A non-transitory computer program product for running on a programmable apparatus, at least including code portions for performing steps of a method when run on a programmable apparatus, the method comprising:
supporting a first virtual machine on a first processor core;
supporting a second virtual machine on a second processor core;
supporting a hypervisor capable of communicating with the first and second virtual machines;
supporting a peripheral device shareable between the first and second virtual machines through an interface of the peripheral device, the interface comprising a set of registers;
supporting a conflict detection circuit capable of communicating with the hypervisor and the first and second virtual machines,
wherein the conflict detection circuit is arranged to support a first and a second virtual image of the set of registers, each virtual image containing a set of register images each mapped to corresponding ones of the set of registers, wherein the first virtual image is associated with the fir

Assignees

• Baumeister Markus
• Steinert Frank
• Nxp Usa Inc

Inventors

• Baumeister Markus
• Steinert Frank

Classifications

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G05B2219/2205

  Multicore · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F9/526 Primary

  Mutual exclusion algorithms · CPC title

• G06F2009/45591

  Monitoring or debugging support · CPC title