Processor with memory-embedded pipeline for table-driven computation

Patent metadata

Field	Value
Publication number	US-9740497-B2
Application number	US-201314053978-A
Country	US
Kind code	B2
Filing date	Oct 15, 2013
Priority date	Sep 6, 2013
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction.

First claim

What is claimed is:

1. A method implemented by a processor to obtain computation results, the method comprising:
storing, in a unified reuse table, a plurality of entries that include both single instructions and a set of instructions of a trace, each entry of the plurality of the entries corresponding with a computation instruction and including values of operands of the computation instruction and an output of the computation instruction, and, based on the computation instruction being one of the set of instructions of the trace, an indication of a subsequent instruction in the trace, wherein based on the computation instruction being one of the set of instructions of the trace, in at least one of the plurality of entries, the values of the operands include the output of a previous computation instruction that is a previous instruction of the set of instructions of the trace;
performing a computation, using a functional unit, based on a corresponding instruction; and
obtaining a result associated with an input based on either or both of the unified reuse table and the functional unit.

2. The method according to claim 1 , further comprising storing the corresponding instruction and a result of the computation performed by the functional unit in the unified reuse table as a new entry.

3. The method according to claim 1 , further comprising the functional unit performing a set of computations corresponding with the set of instructions of the trace and storing the set of instructions and results of the set of computations in the unified reuse table as new entries, each new entry comprising the names corresponding with the values of operands of the corresponding instruction among the set of instructions and the indication of the subsequent instruction in the set of instructions.

4. The method according to claim 1 , wherein the obtaining the result of the input includes obtaining the result from an entry among the plurality of entries of the unified reuse table corresponding with the input instead of from the functional unit.

5. The method according to claim 1 , wherein the obtaining the result of the input includes obtaining a first result associated with the input from the unified reuse table in parallel with obtaining a second result by performing an input computation corresponding with the input using the functional unit.

6. The method according to claim 5 , further comprising verifying the functional unit by comparing the first result with the second result, wherein when the first result and the second result are not equal, a fault is indicated in the functional unit.

7. The method according to claim 1 , further comprising implementing processor logic to select whether an input will be searched among the plurality of entries of the unified reuse table.

8. The method according to claim 1 , further comprising searching among the plurality of entries of the unified reuse table using an input word divided into a first partial word and a second partial word, wherein the searching for each of the first partial word and the second partial word is performed in parallel or serially.

9. The method according to claim 1 , wherein the unified reuse table is implemented as resistive memory.

10. The method according to claim 1 , further comprising forming the processor as a three-dimensional integrated circuit and implementing the unified reuse table on a first layer and forming the functional unit on a second layer.

11. The method according to claim 1 , wherein each entry of the plurality of entries includes an identifier indicating whether the entry is a function, the function being a set of traces and each trace of the set of traces being a set of computation instructions.

12. The method according to claim 11 , further comprising managing the unified reuse table based on an eviction and retention policy.

13. The method according to claim 12 , further comprising retaining an entry of the plurality of entries based on the policy when the identifier of the entry indicates that the entry is a function.

Assignees

• IBM

Inventors

• Bose Pradip
• Buyuktosunoglu Alper
• Guo Xiaochen
• Hunter Hillery C
• Rivers Jude A
• Srinivasan Vijayalakshmi

Classifications

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/3832

  Value prediction for operands; operand history buffers · CPC title

• G06F9/3808 Primary

  for instruction reuse, e.g. trace cache, branch target cache · CPC title