Processor with memory-embedded pipeline for table-driven computation

Patent metadata

Field	Value
Publication number	US-9740496-B2
Application number	US-201314019763-A
Country	US
Kind code	B2
Filing date	Sep 6, 2013
Priority date	Sep 6, 2013
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction.

First claim

What is claimed is:

1. A processor, comprising:
a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries that include both single instructions and a set of instructions of a trace, each entry of the plurality of entries corresponding with a computation instruction and including values of operands of the computation instruction and an output of the computation instruction, and, based on the computation instruction being one of the set of instructions of the trace, an indication of a subsequent instruction in the trace, wherein based on the computation instruction being one of the set of instructions of the trace, in at least one of the plurality of entries, the values of the operands include the output of a previous computation instruction that is a previous instruction of the set of instructions of the trace; and
a functional unit configured to perform a computation based on a corresponding instruction.

2. The processor according to claim 1 , wherein the functional unit performs the computation and stores the corresponding instruction and a result of the computation in the unified reuse table as a new entry.

3. The processor according to claim 1 , wherein the functional unit performs a set of computations corresponding with the set of instructions of the trace and stores the set of instructions and results of the set of computations in the unified reuse table as new entries, each new entry comprising register names corresponding with the values of operands of the corresponding instruction among the set of instructions and the indication of the subsequent instruction in the set of instructions.

4. The processor according to claim 1 , wherein when an input to the unified reuse table corresponds with an entry among the plurality of entries of the unified reuse table, a result associated with the input is obtained from the unified reuse table instead of from the functional unit.

5. The processor according to claim 1 , wherein when an input to the unified reuse table corresponds with an entry among the plurality of entries of the unified reuse table, a first result associated with the input is obtained from the unified reuse table in parallel with a second result obtained by performing an input computation corresponding with the input with the functional unit.

6. The processor according to claim 5 , wherein the processor verifies the functional unit by comparing the first result with the second result and when the first result and the second result are not equal, a fault is indicated in the functional unit.

7. The processor according to claim 1 , further comprising a selector configured to select whether an input to the unified reuse table will be searched among the plurality of entries of the unified reuse table.

8. The processor according to claim 1 , wherein an input word provided as an input to the unified reuse table is divided into a first partial word and a second partial word and the unified reuse table is searched for a match to the first partial word and the second partial word in parallel or serially.

9. The processor according to claim 1 , wherein the unified reuse table is implemented as resistive memory.

10. The processor according to claim 1 , wherein the processor is formed as a three-dimensional integrated circuit and the unified reuse table is implemented on a first layer and the functional unit is formed on a second layer.

11. The processor according to claim 1 , wherein each entry of the plurality of entries includes an identifier indicating whether the entry is a function, the function being a set of traces and each trace of the set of traces being a set of computation instructions.

12. The processor according to claim 11 , wherein the processor manages the unified reuse table based on an eviction and retention policy.

13. The processor according to claim 12 , wherein, based on the policy, the processor retains an entry of the plurality of entries based on the identifier of the entry indicating that the entry is a function.

Assignees

• IBM

Inventors

• Bose Pradip
• Buyuktosunoglu Alper
• Guo Xiaochen
• Hunter Hillery C
• Rivers Jude A
• Srinivasan Vijayalakshmi

Classifications

• G06F9/3832

  Value prediction for operands; operand history buffers · CPC title

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/3808 Primary

  for instruction reuse, e.g. trace cache, branch target cache · CPC title