Instruction group formation techniques for decode-time instruction optimization based on feedback

Patent metadata

Field	Value
Publication number	US-9740491-B2
Application number	US-201514734825-A
Country	US
Kind code	B2
Filing date	Jun 9, 2015
Priority date	Nov 17, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A technique of processing instructions for execution by a processor includes determining whether a first property of a first instruction and a second property of a second instruction are compatible. The first instruction and the second instruction are grouped in an instruction group in response to the first and second properties being compatible and a feedback value generated by a feedback function indicating the instruction group has been historically beneficial with respect to a benefit metric of the processor. Group formation for the first and second instructions is performed according to another criteria, in response to the first and second properties being incompatible or the feedback value indicating the grouping of the first and second instructions has not been historically beneficial.

First claim

What is claimed is:

1. A method of processing instructions for execution by a processor, comprising:
determining, using grouping logic, whether a first property of a first instruction and a second property of a second instruction in an instruction stream are compatible, wherein the first instruction is a last instruction before a cache boundary and the second instruction is an initial instruction after the cache boundary;
grouping, using the grouping logic, the first instruction and the second instruction in a same decode-time instruction optimization group in response to the first and second properties being compatible and a feedback value generated by a feedback function indicating the same decode-time instruction optimization group has been historically beneficial with respect to a benefit metric of the processor; and
group, using the grouping logic, the first and second instructions in different decode-time instruction optimization groups, in response to the first and second properties being compatible and the feedback value indicating the grouping of the first and second instructions in the same decode-time instruction optimization group has not been historically beneficial.

2. The method of claim 1 , wherein the first and second properties are indicated by fewer instruction bits than is required for a full instruction compare.

3. The method of claim 1 , wherein the first and second instructions are grouped in the different decode-time instruction optimization groups to maximize a number of instructions in instruction groups or minimize a number of instruction groups.

4. The method of claim 1 , wherein the first and second properties are associated with instruction classes.

5. The method of claim 1 , wherein the benefit metric corresponds to performance.

6. The method of claim 1 , wherein the benefit metric corresponds to one of reduced power dissipation, reduced energy consumption, reduced voltage swing, and reduced energy-delay.

7. The method of claim 1 , wherein the first and second properties are associated with instruction registers.

8. The method of claim 1 , wherein the first and second properties are associated with instruction registers and instruction classes.

9. The method of claim 1 , further comprising:
performing decode-time instruction optimization (DTIO) in response to the first and second instructions having compatible properties; and
refraining from performing DTIO in response to the first and second instructions not having compatible properties.

10. The method of claim 9 , further comprising:
collecting information on DTIO effectiveness; and
applying the feedback function to the collected information to generate the feedback value.

11. The method of claim 1 , further comprising:
associating the feedback function with one of a hardware core, a hardware thread, a software context, a software process, or a software thread.

12. The method of claim 11 , further comprising:
in response to a context switch for a thread, process and/or partition, initializing the feedback value.

Assignees

• IBM

Inventors

• Gschwind Michael K
• Salapura Valentina

Classifications

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3853

  of compound instructions · CPC title

• G06F9/382

  Pipelined decoding, e.g. using predecoding · CPC title