Solid-state storage management

Patent metadata

Field	Value
Publication number	US-9740439-B2
Application number	US-201113336385-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The solid-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address.

First claim

What is claimed is:

1. A system comprising:
a main board and a solid-state storage board separate from the main board,
the main board being located on a host computer,
the main board coupled to the solid-state storage board via an interface bus,
the solid-state storage board including an address translation module, a solid-state memory device, and flash memory devices,
the flash memory devices including a plurality of physical memory locations identified by physical addresses,
the flash memory devices including a first flash memory device,
the system configured to split a management complexity of the first flash memory device between the main board, the solid-state storage board, and the address translation module,
the solid-state storage board configured to perform a first portion of the management complexity, which includes:
perform, via the address translation module, acceleration operations with respect to translations between logical addresses and physical addresses,
receive a status request of the solid-state storage board and determine whether a request to read data is clear to send in response to the status request of the solid-state storage board, wherein the request includes a first logical address,

retrieve valid pages within data from a first physical address on the first flash memory device, and
write in the flash memory devices write data into a physical location identified by the first physical address;

the main board configured to perform a second portion of the management complexity, which includes:
receive a write request that includes the first logical address and the write data;
establish, externally to the solid-state storage board, a correspondence between the first logical address and the first physical address on the first flash memory device,
wherein the establishing of the correspondence between the first logical address and the first physical address is responsive to the write request,
provide the correspondence to the solid-state storage board, and
store the correspondence in a location on the solid-state memory device, wherein the location is accessible by the address translator module; and

the address translator module configured to facilitate a read physical address flash operation from the first flash memory device and provide low latency and high bandwidth delivery of flash commands to the first flash memory device by translating the first logical address to the first physical address on the first flash memory device based on the correspondence, the translation of the first logical address by the address translator module is responsive to the request to read the data received by the system,
wherein the acceleration operations include utilizing an error correction coding of an error correction code decoder and a table to support the translations between logical addresses and physical addresses,
wherein the establishment of the correspondence between the first logical address and the first physical address is responsive to a projected performance of the main board and characteristics of at least one of the flash memory devices to account for a location of prior errors outputted by the error correction code decoder,
wherein the acceleration operations include the primary error correction code and redundant array of independent disks acceleration operations to support the writing of the write data and to avoid implementing a second portion of the management complexity by the solid-state storage board,
wherein the acceleration operations includes a garbage collection operation comprising:
finding a best candidate to erase during the garbage collection operation, the best candidate is a block with a least number of valid pages,
queuing a read physical address flash operation for the valid pages within the block, and
queuing physical addresses of the valid pages to be erased, and
queuing a write of the valid pages and logical addresses returned by a physical read.

Assignees

• Franceschini Michele M
• Jagmohan Ashish
• IBM

Inventors

• Franceschini Michele M
• Jagmohan Ashish

Classifications

• G06F3/0688 Primary

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7211

  Wear leveling · CPC title