Drive array policy control

Patent metadata

Field	Value
Publication number	US-9740426-B2
Application number	US-201414491770-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Sep 19, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An apparatus can include an interface; cache memory; a plurality of drives; and a controller that includes detection circuitry, a write through mode and a write back mode, where the write through mode writes information received via the interface to the plurality of drives, where the write back mode writes information received via the interface to the cache memory and writes information written to the cache memory to the plurality of drives, and where the detection circuitry selects the write through mode based at least in part on detection of a first condition and selects the write back mode based at least in part on detection of a second condition, where the first condition and the second condition differ.

First claim

What is claimed is:

1. An apparatus comprising:
an interface;
volatile cache memory;
a plurality of non-volatile drives; and
a controller that comprises detection circuitry, a write through mode and a write back mode, and a consistency check mode,
wherein the write through mode writes information received via the interface to the plurality of non-volatile drives,
wherein the write back mode writes information received via the interface to the volatile cache memory and writes information written to the volatile cache memory to the plurality of non-volatile drives, and
wherein the detection circuitry automatically selects the write through mode and enables the consistency check mode based at least in part on detection of a first condition and automatically selects the write back mode and disables the consistency check mode based at least in part on detection of a second condition, wherein the first condition and the second condition differ; and
wherein the first condition comprises a first rate of input operations for writing information received via the interface and wherein the second condition comprises a second rate of input operations for writing information received via the interface wherein the second rate exceeds the first rate.

2. The apparatus of claim 1 wherein the first rate of input operations is below a rate threshold.

3. The apparatus of claim 1 wherein the second rate of input operations exceeds a rate threshold.

4. The apparatus of claim 1 wherein the detection circuitry automatically selects the write through mode based at least in part on detection of a first power state condition and automatically selects the write back mode based at least in part on detection of a second power state condition, wherein the first power state condition and the second power state condition differ.

5. The apparatus of claim 4 wherein the first power state condition is an unstable power state condition.

6. The apparatus of claim 4 wherein the second power state condition is a stable power state condition.

7. The apparatus of claim 1 wherein the detection circuitry automatically selects the write through mode based at least in part on detection of a first environmental state condition and automatically selects the write back mode based at least in part on detection of a second environmental state condition, wherein the first environmental state condition and the second environmental state condition differ.

8. The apparatus of claim 7 wherein the first environmental state condition that corresponds to an unstable power state.

9. The apparatus of claim 7 wherein the second environmental state condition that corresponds to a stable power state.

10. The apparatus of claim 1 wherein the detection circuitry adjusts at least one parameter value based at least in part on a detected condition, wherein the at least one parameter value comprises a threshold parameter value, and wherein the detection circuitry selects the write through mode or the write back mode based at least in part on the threshold parameter value.

11. The apparatus of claim 1 wherein the detected condition comprises a time.

12. The apparatus of claim 11 comprising a schedule that comprises at least one scheduled write through mode time.

13. The apparatus of claim 11 comprising a schedule that comprises at least one scheduled write back mode time.

14. One or more non-transitory computer-readable storage media comprising processor-executable instructions, the instructions comprising instructions to:
detect a first condition;
detect a second, different condition; and
automatically select a write through mode and enable a consistency check mode responsive to detection of the first condition and automatically select a write back mode and disable the consistency check mode responsive to detection of the second condition wherein the write through mode writes information received via an interface to a plurality of non-volatile drives wherein the write back mode writes information received via the interface to volatile cache memory and writes information written to the volatile cache memory to the plurality of non-volatile drives and wherein the first condition comprises a first rate of input operations for writing information received via the interface and wherein the second condition comprises a second rate of input operations for writing information received via the interface wherein the second rate exceeds the first rate.

15. The one or more non-transitory computer-readable storage media of claim 14 wherein the instructions comprise instructions to: adjust at least one parameter value based at least in part on a detected condition wherein at least one of the automatic selections occurs based at least in part on the at least one parameter value.

16. A method comprising:
receiving information via an interface of a server wherein the server comprises a host processor, a redundant array drive controller, and a baseboard management controller;
in a write back mode with a consistency check mode disabled, writing the information to cache memory of the server and writing the information from the cache memory to a plurality of drives of the server that form the redundant array;
receiving additional information via the interface;
detecting a condition via the redundant array drive controller by receiving information from the baseboard management controller of the server; and
responsive to the condition, in a write through mode with the consistency check mode enabled, writing the additional information directly to the plurality of the drives.

17. The method of claim 16 wherein the condition comprises a rate of input operations.

18. The method of claim 16 wherein the consistency check mode comprises verifying correctness of information in at least a portion of the redundant array at least in part by comparing to content of a parity drive in the redundant array.

Assignees

• Lenovo Singapore Pte Ltd

Inventors

• Lee-Baron Jennifer J
• Rose Amy Leigh
• Peterson Nathan J
• Crowe John Scott

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0689

  Disk arrays, e.g. RAID, JBOD · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/065 Primary

  Replication mechanisms · CPC title