Control apparatus and control method

Patent metadata

Field	Value
Publication number	US-9740404-B2
Application number	US-201314771951-A
Country	US
Kind code	B2
Filing date	May 31, 2013
Priority date	May 31, 2013
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A control apparatus, which is configured to control a plurality of processors corresponding to a plurality of storage areas arranged at an interface for accessing the storage areas, comprises: an update unit configured to, in a case a command sequence including each command outputted to one of the storage areas is inputted, update, by each one of the processors, a load applied by a command currently being executed to the storage area corresponding to the processor; a selection unit configured to, for one command of the command sequence, based on a load applied by a command currently executed at the processor updated by the update unit, select a processor out of the processors as an allocation destination of the one command; and an output unit configured to output the one command to the processor selected by the selection unit.

First claim

What is claimed is:

1. A control apparatus configured to control a plurality of processors, corresponding to a plurality of storage areas that are arranged at an interface, for accessing the storage areas, the apparatus comprising:
a memory storing respective load information for each of the plurality of processors;
an update unit configured to, upon receiving an input of a command sequence including two or more commands, wherein each of the two or more commands is to be output to a storage area, update the load information for each processor based on a load applied by a command currently being executed to the storage area corresponding to the processor;
a determination unit configured to determine whether two consecutive commands of the command sequence are of a same type and whether respective addresses for accessing the storage areas of the consecutive commands have continuity,
a selection unit configured to:
if the determination unit determines that the two consecutive commands of the command sequence are of the same type and respective addresses for accessing the storage areas of the two consecutive commands have continuity, select a processor, of the plurality of processors, as an allocation destination of a second command, that is immediately after a first command of the two consecutive commands, that is a same processor as previously selected for the first command, and
if the determination unit determines that the two consecutive commands of the command sequence are not of the same type or respective addresses for accessing the storage areas of the two consecutive commands do not have continuity, select a processor, of the plurality of processors, as an allocation destination of the second command based on the load information of the plurality of processors; and
an output unit configured to output the second command to the processor selected by the selection unit.

2. The control apparatus according to claim 1 ,
wherein the apparatus includes a storage unit configured to store association information correlating identification information of a specified processor out of the plurality of processors with identification information of a specified storage area out of the storage areas being an access destination of the specified processor,
wherein the determination unit is further configured to: by referring to the association information, determine whether identification information of the storage area being an access destination of the second command matches identification information of the specified storage area for the first command, and
wherein the selection unit selects the specified processor in a case the determination unit determines the identification information of the storage area being an access destination of the second command matches the identification information of the specified storage area.

3. The control apparatus according to claim 1 ,
wherein the apparatus includes a storage unit configured to store association information correlating identification information of a specified processor out of the processors with a size of a command outputted by the specified processor to an access destination,
wherein the determination unit is further configured to, by referring to the association information, determine whether a size of the second command matches the size of a command outputted by the specified processor to an access destination, and
wherein the selection unit selects the specified processor in a case the determination unit determines a size of the second command matches a size of a command outputted by the specified processor.

4. A control method for a control apparatus configured to control a plurality of processors, corresponding to a plurality of storage areas that are arranged at an interface, for accessing the plurality of storage areas, the control apparatus including a memory storing respective load information for each of the plurality of processors, the method comprising:
updating, upon receiving an input of a command sequence including two or more commands, wherein each of the two or more commands is to be output to a storage area, the load information for each of the plurality of processors based on a load applied by a command currently being executed to the storage area corresponding to the processor;
determining whether two consecutive commands of the command sequence are of a same type and whether respective addresses for accessing the storage areas of the consecutive commands have continuity,
selecting, if the determination unit determines that the two consecutive commands of the command sequence are of the same type and respective addresses for accessing the storage areas of the consecutive commands have continuity, a processor, of the plurality of processors, as an allocation destination of a second command, that is immediately after a first command of the two consecutive commands, that is a same processor as previously selected for the first command, and selecting, if the determination unit determines that the two consecutive commands of the command sequence are not of the same type or respective addresses for accessing the storage areas of the two consecutive commands do not have continuity, select a processor, of the plurality of processors, as an allocation destination of the second command, based on the load information of the plurality of processors; and
outputting the second command to the processor selected by the selecting.

5. The control method according to claim 4 ,
wherein the apparatus includes a storage unit configured to store association information correlating identification information of a specified processor out of the plurality of processors with identification information of a specified storage area out of the storage areas being an access destination of the specified processor,
wherein the method further comprises the steps of: determining, by referring to the association information, whether identification information of the storage area being an access destination of the second command matches identification information of the specified storage area for the first command, and
wherein, in the selecting, the control apparatus selects the specified processor in a case the determination process determines the identification information of the storage area being an access destination of the second command matches the identification information of the specified storage area.

6. The control method according to claim 4 ,
wherein the apparatus includes a storage unit configured to store association information correlating identification information of a specified processor out of the plurality of processors with a size of a command outputted by the specified processor to an access destination,
wherein the method further comprises the steps of:
determining, by referring to the association information, whether a size of the second command matches the size of a command outputted by the specified processor to an access destination, and
wherein, in the selecting, the control apparatus selects the specified processor in a case the control apparatus determines a size of the second command matches a size of a command outputted by the specified processor.

7. The control method according to claim 4 ,
wherein the type of a command is one of a read and a write command.

8. The control apparatus according to claim 1 ,
wherein the type of a command is one of a read and a write command.

Assignees

• Hitachi Ltd

Inventors

• Kiyota Yusaku
• Gotou Tetsuhiro
• Toyohara Yoshihiro

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0689

  Disk arrays, e.g. RAID, JBOD · CPC title

• G06F3/0613 Primary

  in relation to throughput · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title