USB power delivery dead-battery control

Patent metadata

Field	Value
Publication number	US-9740261-B2
Application number	US-201514841119-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A method of power delivery. Port controllers each include a state machine, an IO pin, a receptacle supply pin receiving power from a receptacle, and a gate driver pin coupled to a control node of a power path switch each having an output coupled to a load. The state machines implement a dead-battery control (DBC) algorithm upon sensing a DB condition. The DBC algorithm pulls up the IO pin, starts a timer for T 1, and monitors the IO pin for T 1. If the IO pin is pulled low, the port controller is reset for a pulled low period, the DBC algorithm is then restarted or its IO pin is monitored until not pulled low for T 1. One port controller pulls its IO pin low for an assertion period to claim priority over the other port controller, and closes its associated power path switch to exclusively provide power to the load.

First claim

The invention claimed is:

1. A method of power delivery, comprising:
providing a first port controller and at least a second port controller each including a state machine, an input/output (IO) pin, at least one receptacle supply pin (V BUS pin and/or V PWR pin) coupled to receive power from a voltage bus (V BUS ) output pin of a receptacle, a VDD supply pin coupled to a VDD supply, and a gate driver pin coupled to one or more control nodes of at least one power path switch that has an output coupled to a power system sink, said first and second port controllers each having a control input coupled to a control output of a processor which serves as their master;
said state machine implementing a dead-battery control (DBC) algorithm upon sensing a dead-battery condition comprising sensing a voltage on said receptacle supply pin and a lack of voltage on said VDD supply pin, said DBC algorithm:
pulling up said IO pin;
starting a timer set for a time period T 1 (T 1 timer) and monitoring said IO pin for said T 1 ;
wherein if said IO pin is pulled low resetting said first port controller or said second port controller for a pull low period and then restarting said DBC algorithm or continuing said monitoring of said IO pin until said IO pin is not pulled low for at least said T 1 so that said T 1 timer expires;
said first port controller or said second port controller pulling its said IO pin low for an assertion period of time to claim priority over another of said first and said second port controller, and
sending a control signal by turning on said gate driver pin to close its associated one of said power path switches to exclusively provide said power to said power system sink.

2. The method of claim 1 , wherein said receptacle comprises a Universal Serial Bus (USB) Type-C receptacle.

3. The method of claim 1 , wherein said IO pin of said first port controller is directly connected to said IO pin of said second port controller.

4. The method of claim 1 , wherein said IO pin and said receptacle supply pin are cross-connected between said first port controller and said second port controller through a MOSFET for pulling said receptacle supply pin low from one of said port controllers when said IO pin of another of said port controllers is low.

5. The method of claim 1 , further comprising repeating said pulling its said IO pin low periodically with a period (tCycle) based a unique Inter Integrated Circuit Communications (I2C) slave address hard coded into said first port controller and said second port controller for preventing another of said first or said second port controller from turning on said gate driver pin.

6. The method of claim 1 , wherein a current received from a power source is determined to be below a minimum threshold current level, entering a low power mode for a predetermine period of time then resetting.

7. The method of claim 5 , wherein said tCycle is based on said I2C slave address.

8. The method of claim 5 , wherein said first port controller and said second port controller are each integrated circuits (ICs) formed on a substrate having a silicon surface.

9. A port controller, comprising:
a state machine;
an input/output (TO) pin, at least one receptacle supply pin for receiving power from a voltage bus (V BUS ) output pin of a receptacle;
a VDD supply pin for coupling to a VDD supply, and a gate driver pin for driving one or more control nodes of at least one power path switch that has an output coupled to a power system sink;
a control input (I2C) for coupling to a control output of a processor which serves a master;
said state machine implementing a dead-battery control (DBC) algorithm upon sensing a DB condition comprising sensing a voltage on said receptacle supply pin and a lack of voltage on said VDD supply pin, said DBC algorithm for implementing:
pulling up said IO pin;
starting a timer set for a time period T 1 (T 1 timer) and monitoring said IO pin for said T 1 ;
wherein if said IO pin is pulled low resetting for a pull low period and then restarting said DBC algorithm or continuing said monitoring of said IO pin until said IO pin is not pulled low for at least said T 1 so that said T 1 timer expires;
pulling its said IO pin low for an assertion period of time to claim priority over another port controller that has another gate driver pin for driving one or more control nodes of at least another power path switch that has another output also coupled to said power system sink, and
sending a control signal by turning on said gate driver pin to close said power path switch to exclusively provide said power to said power system sink.

10. The port controller of claim 9 , wherein said DBC algorithm is for further implementing repeating said pulling its said IO pin low periodically with a period (tCycle) based a unique Inter Integrated Circuit Communications (I2C) slave address hard coded therein for preventing said another port controller from turning on said another gate driver pin.

11. The port controller of claim 9 , wherein said DBC algorithm is for further implementing wherein a current received from a power source is determined to be below a minimum threshold current level, entering a low power mode for a predetermine period of time then resetting.

12. The port controller of claim 10 , wherein said tCycle is based on said I2C slave address.

13. The port controller of claim 9 , wherein said port controller is an integrated circuit (IC) formed on a substrate having a silicon surface.

Assignees

• Texas Instruments Inc

Inventors

• Waters Deric Wayne
• Hastings Roy Alan

Classifications

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F1/266 Primary

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

• G06F1/30 Primary

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title